Multi-Tech MultiConnect mDot MTDOT Series, Developer'S Manual

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DESIGN CONSIDERATIONS
MultiConnect
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mDot
TM
MTDOT Developer Guide for Japan 59
Chapter 14 – Design Considerations
Noise Suppression Design
Adhere to engineering noise-suppression practices when designing a printed circuit board (PCB). Noise suppression
is essential to the proper operation and performance of the modem and surrounding equipment.
Any OEM board design must consider both on-board and off-board generated noise that can affect digital signal
processing. Both on-board and off-board generated noise that is coupled on-board can affect interface signal levels
and quality. Noise in frequency ranges that affect modem performance is of particular concern.
On-board generated electromagnetic interference (EMI) noise that can be radiated or conducted off-board is
equally important. This type of noise can affect the operation of surrounding equipment. Most local government
agencies have certification requirements that must be met for use in specific environments.
Proper PC board layout (component placement, signal routing, trace thickness and geometry, and so on)
component selection (composition, value, and tolerance), interface connections, and shielding are required for the
board design to achieve desired modem performance and to attain EMI certification.
Other aspects of proper noise-suppression engineering practices are beyond the scope of this guide. Consult noise
suppression techniques described in technical publications and journals, electronics and electrical engineering text
books, and component supplier application notes.
PC Board Layout Guideline
In a 4-layer design, provide adequate ground plane covering the entire board. In 4-layer designs, power and ground
are typically on the inner layers. Ensure that all power and ground traces are 0.05 inches wide.
The recommended hole size for the device pins is 0.036 in. +/-0.003 in. in diameter. Use spacers to hold the device
vertically in place during the wave solder process.
Electromagnetic Interference
The following guidelines are offered specifically to help minimize EMI generation. Some of these guidelines are the
same as, or similar to, the general guidelines. To minimize the contribution of device-based design to EMI, you
must understand the major sources of EMI and how to reduce them to acceptable levels.
Keep traces carrying high frequency signals as short as possible.
Provide a good ground plane or grid. In some cases, a multilayer board may be required with full layers for
ground and power distribution.
Decouple power from ground with decoupling capacitors as close to the device's power pins as possible.
Eliminate ground loops, which are unexpected current return paths to the power source and ground.
Decouple the telephone line cables at the telephone line jacks. Typically, use a combination of series
inductors, common mode chokes, and shunt capacitors. Methods to decouple telephone lines are similar to
decoupling power lines; however, telephone line decoupling may be more difficult and deserves additional
attention. A commonly used design aid is to place footprints for these components and populate as
necessary during performance/EMI testing and certification.
Decouple the power cord at the power cord interface with decoupling capacitors. Methods to decouple
power lines are similar to decoupling telephone lines.