3.5.2.19 PC/104 Interface Connector (J29/J36)
For more detailed information please refer to the PC/104 Specification, V2.5 and to the IEEE P996 draft
standard (D2.02).
Pin
Row A
Row B
Row C
Row D
Pin Assignment
0
--
--
GND
GND
1
/IOCHCK
GND
/SBHE
/MEMCS16
2
SD7
RSTDRV
LA23
/IOCS16
3
SD6
+5 V
LA22
IRQ10
4
SD5
IRQ9
LA21
IRQ11
5
SD4
(-5 V)
*1
LA20
IRQ12
6
SD3
NC (DRQ2)
LA19
IRQ15
7
SD2
(-12 V)
*1
LA18
IRQ14
8
SD1
Pull-up (/ENDXFR)
*2
LA17
pull-up (/DACK0)
*2
9
SD0
(+12 V)
*1
/MEMR
NC (DRQ0)
*2
10
IOCHRDY
NC
/MEMW
pull-up (/DACK5)
*2
11
AEN
/SMEMW
SD8
NC (DRQ5)
*2
12
SA19
/SMEMR
SD9
pull-up (/DACK6)
*2
13
SA18
/IOW
SD10
NC (DRQ6)
*2
14
SA17
/IOR
SD11
pull-up (/DACK7)
*2
15
SA16
pull-up (/DACK3)
SD12
NC (DRQ7)
*2
16
SA15
NC (DRQ3)
*2
SD13
+5 V
17
SA14
pull-up (/DACK1)
*2
SD14
pull-up (/MASTER)
*2
18
SA13
NC (DRQ1)
*2
SD15
GND
19
SA12
/REFRESH
NC
GND
20
SA11
SYSCLK
--
--
21
SA10
IRQ7
--
--
22
SA9
IRQ6
--
--
23
SA8
IRQ5
--
--
24
SA7
IRQ4
--
--
25
SA6
IRQ3
--
--
26
SA5
pull-up (/DACK2)
*2
--
--
27
SA4
TC
--
--
28
SA3
BALE
--
--
29
SA2
+5 V
--
--
30
SA1
14.318 MHz Clock
--
--
31
SA0
GND
--
--
32
GND
GND
--
--
DC
AB
1
0
19
32
Figure 44:
PC/104 Connector
(Connector: Samtec, ESW-120-12GD /
ESW-132-12GD)
Notes:
For the maximum allowed current on each voltage please refer to chapter 3.7.
*1
-12 V, -5 V and 12 V are only available if supplied to the Internal Power Connector 1 (J4) from a power supply
(please refer to chapter 3.5.2.11 and 3.7).
*2
Signal not used or not available. ISA DMA cycles (with DRQ, DACK signals) and ISA Master cycles (with /MASTER
signal) are not supported in the PIP20 design.
2010 by MPL AG
39
MEH-10126-201 Rev. D
High-Tech • Made in Switzerland
PIP20 / PIP22
Technical Reference Manual
