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Motorola SPX3BUM/D, User Manual

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Motorola SPX3BUM/D User Manual Download Page 9

MOTOROLA

  

9

3.1.1 ROMSEL

The “ROMSEL” switch may be used to select between the primary and secondary flash device (if any) on
the Sandpoint 3.

NOTE: Not all Sandpoint 3’s have a secondary flash.

NOTE: The RMODE switch (see Section 3.3.2) overrides this switch.

3.1.2 ROM1WP

The “ROM1WP” switch may be used to write-protect the secondary (backup) PCI-hosted boot ROM, if any.
This primary ROM normally contains the DINK debugger, but with the backup ROM protected, users may
overwrite the boot ROMs with development code and still return to DINK as a backup measure.

NOTE: Not all Sandpoint 3’s have a secondary flash.

3.1.3 Reserved

Switch SW2-3 is reserved and has no function.

7

SSRNG

Spread-Spectrum Range

8

PSON

Force Power Supply ON

Table 2. Sandpoint 3 ROMSEL Option

ROMSEL

Definition

Notes

SW1-1

On (right)

Primary ROM (29F040) is used for PCI boot 

option.

Normal mode.

Off (left)

Secondary ROM (28F800) is used for PCI boot 

option.

Table 3. Sandpoint 3 ROM1WP Switch

ROM1WP

Definition

Notes

SW1-2

On (right)

ROM1 may be read to or written from.

Use to store OS code.

Off (left)

ROM1 is write-protected.

Table 1. Sandpoint 3 SW1 Options

Switch

Name

Definition

Default

Summary of Contents for SPX3BUM/D

Page 1: ...numerous processor specific PPMC cards but just one at a time This user s manual covers the following issues Topic Page Section 1 Introduction 2 Section 2 Setup 4 Section 3 Configuration 7 Section 4 Programmers Model 16 Section 5 Initializing Sandpoint 22 Section 6 Development Issues 23 Section 7 Troubleshooting 27 Section 8 FAQ 30 To locate any published errata or updates for this document refer ...

Page 2: ...supplies typical PC I O peripherals Sandpoint provides a flexible base for the evaluation of new Motorola processor devices and for early software design for customer project using Motorola processors Figure 1 shows a block diagram of the Sandpoint III system Figure 1 Sandpoint III Block Diagram Motorola MPMC Board PCI Slots Winbond IDE IDE SuperIO KBD MSE SPF100 COM1 COM2 PAR FLP ROM1 ROM2 NVRM ...

Page 3: ...erial ports IEEE 1284 parallel port Floppy disk port Two ATA33 bus master IDE ports PS 2 mouse and keyboard connectors BBVRAM 8K bytes Real Time Clock Switch selectable operating modes Advanced Power Controller soft on off LED monitors for critical functions The I O subsystem is identical to that of the Sandpoint 2 and the EC version of the older Yellowknife development platform When properly conf...

Page 4: ...sing the supplied AC power code For international operation at 240 VAC replace the connector with an appropriately keyed power cable STEP 2 Turn the power supply on using the switch at the back of the Sandpoint chassis near the power cord The system will not turn on at this time STEP 3 Attach a null modem cable between the Sandpoint COM1 port top most as shown in Figure 2 to the PC or workstation ...

Page 5: ...em Sandpoint with Altimus Talos MPMC60x 7xx 74xx Processor MPC7400 V2 8 500 MHz Memory 100 MHz Memory Map B CHRP 00000000 03FFFFFF Copyright Motorola Inc 1993 2001 Refer to history c for release info changes errata and fixes DINK32_MAX At this point DINK is ready to accept user commands such as downloading and starting code or assembling user programs Refer to the DINK User s Manual for more detai...

Page 6: ...dem cable is required These cables are readily available from computer supply stores In addition it is simple to make as shown in Figure 3 Figure 3 Null Modem Diagram Once the cable is available or constructed attach one end to the Sandpoint COM1 port and the other to the PC Workstation Either end will work with either computer DB9 Female Back View 1 5 9 6 2 3 4 8 7 DB9 Female Back View 1 5 9 6 2 ...

Page 7: ... development platform Configurable features include Using an external PCI arbiter instead of the PMC resident arbiter Using the 8259 PIC in the Winbond instead of the PMC interrupt controller PnP Plug and Play PC I O devices can remain uninitialized and virtually disappear Another reason to change the configuration is to use the legacy modes for Sandpoint 2 compatibility Refer to Appendix A for de...

Page 8: ...a system power on reset The system pushbutton reset is not necessarily sufficient 3 1 SW1 Options SW1 is located near the bottom of the Sandpoint 3 board near the end of the fourth PCI slot It controls the features shown in Table 1 Table 1 Sandpoint 3 SW1 Options Switch Name Definition Default 1 ROMSEL ROM Selection 2 ROM1WP ROM1 Write Protect 3 reserved reserved 4 FRCPCI33 Force PCI to 33MHz 5 EX...

Page 9: ...the boot ROMs with development code and still return to DINK as a backup measure NOTE Not all Sandpoint 3 s have a secondary flash 3 1 3 Reserved Switch SW2 3 is reserved and has no function 7 SSRNG Spread Spectrum Range 8 PSON Force Power Supply ON Table 2 Sandpoint 3 ROMSEL Option ROMSEL Definition Notes SW1 1 On right Primary ROM 29F040 is used for PCI boot option Normal mode Off left Secondary...

Page 10: ...Hz or 66 MHz frequencies supported The clock source must be attached to the coaxial SMA connector on the board and the clock signal supplied must meet the requirements listed in Table 6 NOTE Care must be used that the devices receiving the clock are capable of and are configured to operate at the new clock speed In particular Motorola processors have internal PLLs which require a minimum clock inp...

Page 11: ... AC power is applied to the system power supply Normally the system power is controlled with the APC in the SuperIO chip and power is controlled through the chassis switch motherboard pushbutton or APC under software control If PSON is selected the system remains on until external power is removed Table 7 Sandpoint 3 SSCLK Switch SSCLK Definition Notes SW1 6 On right PCI clocks are modulated by 1 ...

Page 12: ...lemented the AMODE arbitration mode select switches These options are no longer supported and older SP3 systems should be upgraded SP3 exclusively uses the Winbond as the system arbiter requests are assigned as follows WB_REQ 0 PMC_REQ 0 WB_REQ 1 SLOT_REQ 1 WB_REQ 2 SLOT_REQ 2 WB_REQ 3 SLOT_REQ 3 WB_REQ 4 SLOT_REQ 4 And grants are handled correspondingly Table 10 Sandpoint 3 SW2 Options Switch Nam...

Page 13: ...would normally be possible with the four allocated pins shows the serial slot corresponding to each external interrupt Table 11 Sandpoint 3 ILEGACY Switches ILEGACY Definition Notes SW2 3 On right Standard SP3 Interrupt Modes Default Off left Legacy Sandpoint 1 2 Interrupt Modes See Appendix B Table 12 Sandpoint 3 IMode Switches IMODE 0 1 Definition Notes SW2 4 SW2 5 On right On right Serial Defau...

Page 14: ... on updated SPX3 systems with serial numbers after 5150 When IMODE is set such that the Slots option is selected the MPMC will accept interrupts from the four PCI slots and ignore the Winbond and SuperIO devices This mode is appropriate for systems which will not be using such devices and want all PCI slot interrupts Interrupts are connected as shown in Table 14 For single interrupt cards the vast...

Page 15: ...kes no use of these switch settings they are provided for user defined functions See Section 4 for details on reading the GPIO port Table 15 Sandpoint 3 RMode Switches RMODE Definition Notes SW2 6 On right ROMSEL governs ROM Flash access Default Off left Primary ROM 0xFFF0_0000 0xFFFF_FFFF Secondary ROM 0xFF80_0000 0xFFEF_FFFF Table 16 Sandpoint 3 USER Switches USER 0 1 Definition Notes SW2 7 SW2 ...

Page 16: ...SA I O devices appear in this space The detailed address map in Table 18 assumes that the PnP devices have not been changed from the default locations Table 17 Global Address Map START END Definition Notes 0000_0000 3FFF_FFFF SDRAM 1 4000_0000 77FF_FFFF reserved 7800_0000 7BFF_FFFF RCS3 ROM space 2 7C00_0000 7FFF_FFFF RCS2 ROM space 2 8000_0000 FCFF_FFFF PCI memory 3 FD00_0000 FDFF_FFFF PCI ISA me...

Page 17: ...A Controller 1 Clear Byte Pointer FE00_000D W WB DMA Controller 1 Master Clear FE00_000E W WB DMA Controller 1 Clear Mask FE00_000F W WB DMA Controller 1 Write All Mask FE00_0010 FE00_001F unassigned FE00_0020 R W WB PIC 1 Command FE00_0021 R W WB PIC 1 Command FE00_0022 FE00_003F unassigned FE00_0040 R W WB Counter 0 FE00_0041 R W WB Counter 1 FE00_0042 R W WB Counter 2 FE00_0043 W WB Timer Count...

Page 18: ...86 WB DMA Reserved Page FE00_0087 R W WB DMA Memory Page 0 FE00_0088 WB DMA Reserved Page FE00_0089 R W WB DMA Memory Page 6 FE00_008A R W WB DMA Memory Page 7 FE00_008B R W WB DMA Memory Page 5 FE00_008C FF80_008E WB DMA Reserved Page FE00_008F FE00_0091 unassigned FE00_0092 R W WB Port 92 System Reset FE00_0093 FE00_009F unassigned FE00_00A0 R W WB PIC 2 Command FE00_00A1 R W WB PIC 2 Command FE...

Page 19: ...ntroller 2 Request FE00_00D3 unassigned FE00_00D4 W WB DMA Controller 2 Mask FE00_00D5 unassigned FE00_00D6 W WB DMA Controller 2 Mode W FE00_00D7 unassigned FE00_00D8 W WB DMA Controller 2 Clear Byte Pointer FE00_00D9 unassigned FE00_00DA W WB DMA Controller 2 Master Clear FE00_00DB unassigned FE00_00DC W WB DMA Controller 2 Clear Mask FE00_00DD unassigned FE00_00DE W WB DMA Controller 2 Write Al...

Page 20: ..._0400 FE00_0409 unassigned FE00_040A R WB DMA Scatter Gather Interrupt Status FE00_040B W WB DMA Controller 1 Extended Mode FE00_040C FE00_0414 unassigned FE00_0415 W WB DMA Scatter Gather Channel 5 Command FE00_0416 W WB DMA Scatter Gather Channel 6 Command FE00_0417 W WB DMA Scatter Gather Channel 7 Command FE00_0418 FE00_041C unassigned FE00_041D R WB DMA Scatter Gather Channel 5 Status FE00_04...

Page 21: ...ter 1 FE00_0484 FE00_0486 unassigned FE00_0487 R W WB DMA Page Register 0 FE00_0488 unassigned FE00_0489 R W WB DMA Page Register 6 FE00_048A R W WB DMA Page Register 7 FE00_048B R W WB DMA Page Register 5 FE00_048C FE00_04CF unassigned FE00_04D0 R W WB PIC 1 Interrupt Control FE00_04D1 R W WB PIC 2 Interrupt Control FE00_04D2 FE00_06FF unassigned FE00_0700 R W SIO GPIO Port 0 Data 2 FE00_0701 R W...

Page 22: ...ce code Starting with DINK release 12 3 and later a demonstration Sandpoint initialization file spinit s will be available Table 19 Dink Functions Step Functions Source file Notes 1 CPU setup except2 S starting at system_reset 2 BAT setup except2 S starting at mmu_setup 3 Cache setup except2 S cache S starting at init_L2backside_cache all of cache s 4 MPC107 MPC8240 setup mpc107 S or kahlua S All ...

Page 23: ...inary Then the DINK command DINK32_MAX dl k b o 90000 436 bytes transferred DINK32_MAX will initiate a binary download After issuing the dl command use your terminal emulation program to send the file as is no translation padding or flow control DINK stops accepting characters from the terminal program after 5 seconds of inactivity NOTE The basic Hyperterminal program on a PC inserts NULLs every 3...

Page 24: ... code to the ROM on the Sandpoint motherboard but this overwrites DINK itself or to one of the two flashes on most MPMC cards The fupdate command can be used for this purpose Download the code to memory dl k o 100000 and download your program as usual Make sure the PROGMODE switch on the MPMC card is on see the configuration guides for the corresponding MPMC card for switch location Issue the comm...

Page 25: ...ration guide included in the bound documentation or on the Sandpoint website see Appendix C 6 7 Upgrading DINK Occasionally DINK is upgraded with new facilities and bug fixes DINK 12 1 or later has the ability to update itself using the fupdate command To update DINK with a new version follow this sequence 1 Consider making a safety copy of the current DINK first by saving it to the flash on the M...

Page 26: ...ry for faster download as described in Section 6 2 4 Issue the command fu h 100000 fff00000 7ff00 Restart and the new version of DINK should activate If an error occurs DINK will not work and the flash will need to be externally re programmed on a PROM programmer If the safety copy was made in step 1 above just set the ROMLOC switch to boot from the local flash instead of PCI ...

Page 27: ...uivalent is connected to the chassis header J29 on the pins labelled PWR SW pins 24 and 26 If STANDBY POWER is on but neither the front panel power switch nor the internal red button will start DINK set the PSON switch see Section 3 1 8 If power is now available MAIN POWER is on the APC unit is not functioning Make sure that the battery is installed and is not discharged replace if necessary Sandp...

Page 28: ... an external programming system If power is on LEDs are active system is in default configuration and the PCI LED is active continuously DINK is running Check the serial port connections 1 Make sure you are using a null modem cable A standard cable will not work 2 Make sure the cable is in COM1 on the Sandpoint system nearest the power cord 3 Make sure you re using the COM port your terminal expec...

Page 29: ...alized then hangs Make sure DINK is not trying to setup an invalid L2 L3 setting if appropriate or other configuration Press the backspace key and hold it down while pressing RESET If DINK comes up enter the command ENV c DINK runs fine for a while then hangs until it cools down Open the chassis and make sure the heat sink especially those with a fan is firmly attached and that the fan is connecte...

Page 30: ...e device number to the PCI configuration address register 0xFEC0_0000 and reading writing from the PCI configuration data register 0xFEE0_0000 See the file pciLib c in the DINK source code for examples 5 How can I control the STAT and FAIL LEDs To do this the GPIO port in the SuperIO needs to be enabled Use the code in yk c ns308defaults as a starting point This file sets the GPIO programmable add...

Page 31: ...FF7_FFFF On board spread spectrum clock generator None spread spectrum is disabled by default IDE interface corrected None 2 was rewired IDE PCI interrupts connected properly Software may use PCI interrupts instead of 8259 interrupts On board reset controller for more reliable resetting particularly from COP None Cabled battery replaced with standard socketed coin None All PCI bus devices PMC and ...

Page 32: ... INTA INTB SP2 there s not much point emulating SP2 bugs Using the standard modes is highly encouraged as nothing like this will be supported on future Sandpoint platform or any other platform Table 23 Legacy Interrupt Connections SW2 5 SW2 5 Sandpoint 2 Modes Interrupt Connections Notes On right On right 0 inverted interrupt share SLOT2 PMC_INT0 Winbond INTC Winbond IDE can output to INTC INTD SI...

Page 33: ...ry jsp code MPC8240 MPC107 User s Manual http e www motorola com webapp sps site pro d_summary jsp code MPC107 DINK User s Manual and code updates http e www motorola com webapp sps site pro d_summary jsp code DINK32 Draft Standard Physical and Environmental Layers for Processor PCI Mezzanine Cards PrPMC http www vita com vso PCI 2 1 Specification http www pcisig com Draft Standard Physical and En...

Page 34: ...ion proposal which adds PCI arbitration PCI Peripheral Connect Interface PMC PCI Mezzanine Card a small form factor PCI 2 0 compliant daughtercard standard PPMC Processor PCI Mezzanine Card an early name for PrPMC no longer used PrPMC Processor PCI Mezzanine Card an extension to the IEEE1386 PMC standard adding host related functions and PCI 2 1 compatibility was formerly called PPMC RAM Are you k...

Page 35: ...ed in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized...

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