Motorola Semiconductor MC68HC11F1 Technical Manual Download Page 34 | Manualshive

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MOTOROLA

MC68HC11F1/FC0

34

MC68HC11FTS/D

7.7 Port G

Port G is an eight-bit general-purpose I/O port with a data register (PORTG) and a data direction register
(DDRG). When enabled, the upper four lines (PG[7:4] can be used as chip-select outputs in expanded
modes. When any of these pins are not being used for chip selects, they can be used for general-pur-
pose I/O. Port G can be configured for wired-OR operation by setting the GWOM bit in the OPT2 reg-
ister.

NOTE

PG[1:0] are not available on the 64-pin MC68HC11FC0.

7.8 Parallel I/O Registers

Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-
tions, an “I” indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a “U”.

I = Indeterminate value

For DDRx bits, 0 = input and 1 = output.

*These bits are not present on the 64-pin QFP version of the MC68HC11FC0.
I = Indeterminate value

PORTA — Port A Data Register

$x000

Bit 7

6

5

4

3

2

1

Bit 0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

RESET:

I

I

I

I

I

I

I

I

Alternate
Function:

PAI

OC2

OC3

OC4

OC5/IC4

IC1

IC2

IC3

And/or:

OC1

OC1

OC1

OC1

OC1

—

—

—

DDRA — Port A Data Direction Register

$x001

Bit 7

6

5

4

3

2

1

Bit 0

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

DDA0

RESET:

0

0

0

0

0

0

0

0

PORTG — Port G Data Register

$x002

Bit 7

6

5

4

3

2

1

Bit 0

PG7

PG6

PG5

PG4

PG3

PG2

PG1*

PG0*

RESET:

I

I

I

I

I

I

I

I

Alternate
Function:

CSPROG

CSGEN

CSIO1

CSIO2

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Summary of Contents for Semiconductor MC68HC11F1

Page 1: ...h as six MHz This document provides a brief overview of the structure features control registers packaging infor mation and availability of the MC68HC11F1 and MC68HC11FC0 For detailed information on M68HC11 subsystems programming and the instruction set refer to the M68HC11 Reference Manual M68HC11RM AD 1 1 Features MC68HC11 CPU 512 Bytes of On Chip Electrically Erasable Programmable ROM EEPROM wi...

Page 2: ...1F1VPU2 3 MHz MC68HC11F1VPU3 4 MHz MC68HC11F1VPU4 40 to 125 C 2 MHz MC68HC11F1MPU2 3 MHz MC68HC11F1MPU3 4 MHz MC68HC11F1MPU4 68 Pin PLCC 0 to 70 5 MHz MC68HC11F1FN5 40 to 85 C 2 MHz MC68HC11F1CFN2 3 MHz MC68HC11F1CFN3 4 MHz MC68HC11F1CFN4 5 MHz MC68HC11F1CFN5 40 to 105 C 2 MHz MC68HC11F1VFN2 3 MHz MC68HC11F1VFN3 4 MHz MC68HC11F1VFN4 40 to 125 C 2 MHz MC68HC11F1MFN2 3 MHz MC68HC11F1MFN3 4 MHz MC68H...

Page 3: ...U5 0 to 70 C 6 MHz MC68HC11FC0FU6 80 Pin Thin Quad Flat Pack TQFP 40 to 85 C 4 MHz MC68HC11FC0CPU4 5 MHz MC68HC11FC0CPU5 0 to 70 C 6 MHz MC68HC11FC0PU6 Table 4 MC68HC11FC0 Extended Voltage 3 0 to 5 5 V Device Ordering Information Package Temperature Frequency MC Order Number 64 Pin Quad Flat Pack QFP 0 to 70 C 3 MHz MC68L11FC0FU3 4 MHz MC68L11FC0FU4 80 Pin Thin Quad Flat Pack TQFP 3 MHz MC68L11FC0...

Page 4: ...le ROM 29 6 1 EEPROM Operation 29 6 2 EEPROM Registers 29 6 3 EEPROM Programming and Erasure 31 6 4 CONFIG Register Programming 32 7 Parallel Input Output 33 7 1 Port A 33 7 2 Port B 33 7 3 Port C 33 7 4 Port D 33 7 5 Port E 33 7 6 Port F 33 7 7 Port G 34 7 8 Parallel I O Registers 34 8 Chip Selects 38 8 1 Chip Select Operation 38 8 2 Chip Select Registers 38 9 Serial Communications Interface SCI ...

Page 5: ...on Register 2 1038 22 36 52 OPTION System Configuration Options 1039 23 26 56 PACNT Pulse Accumulator Count 1027 66 PACTL Pulse Accumulator Control 1026 63 65 PORTA Port A Data 1000 34 PORTB Port B Data 1004 35 PORTC Port C Data 1006 35 PORTD Port D Data 1008 36 PORTE Port E Data 100A 36 PORTF Port F Data 1005 35 PORTG Port G Data 1002 34 PPROG EEPROM Programming Control 103B 30 SCCR1 SCI Control ...

Page 6: ... 1024 BYTES STATIC RAM CPU CORE DDRD PORT D ACCUMULATOR SCI SPI PD0 PD1 PD2 PD3 PD4 PD5 RxD TxD MISO MOSI SCK SS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORT B ADDR15 ADDR14 ADDR13 ADDR12 ADDR10 ADDR9 ADDR8 PORT F PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR11 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 A...

Page 7: ...EN CSIO1 CSIO2 CHIP SELECTS 1024 BYTES STATIC RAM CPU CORE DDRD PORT D PORT E PE6 PE5 PE4 PE3 PE2 PE1 ACCUMULATOR SCI SPI PD0 PD1 PD2 PD3 PD4 PD5 RxD TxD MISO MOSI SCK SS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORT B ADDR15 ADDR14 ADDR13 ADDR12 ADDR10 ADDR9 ADDR8 PORT F PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR...

Page 8: ... V RL PE7 AN7 PE3 AN3 PE6 AN6 PE2 AN2 PE5 AN5 PC1 DATA1 PC2 DATA2 PC3 DATA3 PC4 DATA4 PC5 DATA5 PC6 DATA6 PC7 DATA7 RESET XIRQ IRQ PG7 CSPROG PG6 CSGEN PG5 CSIO1 PG4 CSIO2 PG3 PG2 PG0 29 PD0 RxD 30 PD1 TxD 31 PD2 MISO 32 PD3 MOSI 33 PD4 SCK 34 PD5 SS 35 V DD 36 PA7 PAI OC1 37 PA6 OC2 OC1 38 PA5 OC3 OC1 39 PA4 OC4 OC1 40 PA3 OC5 IC4 OC1 41 PA2 IC1 42 PA1 IC2 27 PA0 IC3 28 PF3 ADDR3 MC68HC11F1 10 11...

Page 9: ...1 TXD PD0 RXD PG0 NC NC NC 21 NC 22 PE1 AN1 23 PE5 AN5 24 PE2AN2 25 PE6 AN6 26 PE3 AN3 27 PE7 AN7 28 V RL 29 V RH 30 V SS 31 MODB V STBY 32 MODA LIR 33 E 34 R W 35 EXTAL 36 XTAL 37 NC 38 4XOUT 39 PC0 DATA0 40 PG7 CSPROG MC68HC11F1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6...

Page 10: ...ATA2 PC1 DATA1 PD0 RxD PD1 TxD PD2 MISO PD3 MOSI PD4 SCK PD5 SS V DD PA7 PAI OC1 PA6 OC2 OC1 PA5 OC3 OC1 PA4 OC4 OC1 PA3 IC4 OC5 OC1 PA2 IC1 PA1 IC2 PA0 IC3 PB7 ADDR15 PB6 ADDR14 3 PB5 ADDR13 4 PB4 ADDR12 5 PB3 ADDR11 6 PB2 ADDR10 7 PB1 ADDR9 8 PB0 ADDR8 9 PF7 ADDR7 10 PF6 ADDR6 11 PF5 ADDR5 12 PF4 ADDR4 13 PF3 ADDR3 14 PF2 ADDR2 15 PF1 ADDR1 16 PF0 ADDR0 1 VSS 2 DS MC68HC11FC0 49 50 51 52 53 54 5...

Page 11: ...D2 MISO PD3 MOSI PD4 SCK PD5 SS V DD PA7 PAI OC1 PA6 OC2 OC1 PA5 OC3 OC1 PA4 OC4 OC1 PA3 IC4 OC5 OC1 PA2 IC1 PA1 IC2 PA0 IC3 PB7 ADDR15 NC NC 1 NC 2 PB6 ADDR14 3 PB5 ADDR13 4 PB4 ADDR12 5 PB3 ADDR11 6 PB2 ADDR10 7 PB1 ADDR9 8 PB0 ADDR8 9 PF7 ADDR7 10 PF6 ADDR6 11 PF5 ADDR5 12 PF4 ADDR4 13 PF3 ADDR3 14 PF2 ADDR2 15 PF1 ADDR1 16 PF0 ADDR0 17 VSS 18 PE4 19 NC 20 PG0 DS MC68HC11FC0 61 62 63 64 65 66 6...

Page 12: ...next four EXTAL clock cycles If it is low the E clock responds normally going low two EXTAL cycles later The WAIT pin is present on the MC68HC11FC0 only 4XOUT This pin provides a buffered oscillator signal to drive another M68HC11 MCU The 4XOUT pin is not present on the 64 pin QFP MC68HC11FC0 package IRQ This active low input provides a means of generating asynchronous maskable interrupt requests ...

Page 13: ... PC 7 0 In expanded modes port C pins are configured as data bus pins DATA 7 0 Port D Pins Port D is a 6 bit general purpose I O port with a data register PORTD and a data direction register DDRD The six port D lines PD 5 0 can be used for general purpose I O or for the serial communications interface SCI or serial peripheral interface SPI subsystems Port E Pins Port E is an 8 bit input only port ...

Page 14: ...DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD 100A PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTE 100B FOC1 FOC2 FOC3 FOC4 FOC5 0 0 0 CFORC 100C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 0 0 0 OC1M 100D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 0 0 0 OC1D 100E Bit 15 14 13 12 11 10 9 Bit 8 TCNT High 100F Bit 7 6 5 4 3 2 1 Bit 0 TCNT Low 1010 Bit 15 14 13 12 11 10 9 Bit 8 TIC1 High 1011 Bit 7 6 5 4 3 2 1 Bit 0 TIC1 Low 1012 Bit 15 14 13 12 1...

Page 15: ...it 0 ADR1 1032 Bit 7 6 5 4 3 2 1 Bit 0 ADR2 1033 Bit 7 6 5 4 3 2 1 Bit 0 ADR3 1034 Bit 7 6 5 4 3 2 1 Bit 0 ADR4 1035 0 0 0 PTCON BPRT3 BPRT2 BPRT1 BPRT0 BPROT 1036 Reserved 1037 Reserved 1038 GWOM CWOM CLK4X LIRDV 0 SPRBYP 0 0 OPT2 1039 0 0 IRQE DLY CME FCME CR1 CR0 OPTION 103A Bit 7 6 5 4 3 2 1 Bit 0 COPRST 103B ODD EVEN 0 BYTE ROW ERASE EELAT EEPGM PPROG 103C RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1...

Page 16: ...Bit 8 TCNT High 100F Bit 7 6 5 4 3 2 1 Bit 0 TCNT Low 1010 Bit 15 14 13 12 11 10 9 Bit 8 TIC1 High 1011 Bit 7 6 5 4 3 2 1 Bit 0 TIC1 Low 1012 Bit 15 14 13 12 11 10 9 Bit 8 TIC2 High 1013 Bit 7 6 5 4 3 2 1 Bit 0 TIC2 Low 1014 Bit 15 14 13 12 11 10 9 Bit 8 TIC3 High 1015 Bit 7 6 5 4 3 2 1 Bit 0 TIC3 Low 1016 Bit 15 14 13 12 11 10 9 Bit 8 TOC1 High 1017 Bit 7 6 5 4 3 2 1 Bit 0 TOC1 Low 1018 Bit 15 14...

Page 17: ...erved 1038 GWOM CWOM CLK4X LIRDV 0 SPRBYP 0 0 OPT2 1039 0 0 IRQE DLY CME FCME CR1 CR0 OPTION 103A Bit 7 6 5 4 3 2 1 Bit 0 COPRST 103B Reserved 103C RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1 PSEL0 HPRIO 103D RAM5 RAM4 RAM3 RAM2 RAM1 RAM0 REG1 REG0 INIT 103E TILOP 0 OCCR CBYP DISR FCM FCOP 0 TEST1 103F 0 0 0 0 0 NOCOP 0 0 CONFIG 1040 Reserved to 105B Reserved 105C I01SA I01SB I02SA I02SB GSTHA GSTGB PSTH...

Page 18: ...of the CONFIG register In single chip and bootstrap modes the EEPROM is located from FE00 to FFFF 4 1 Operating Modes Bootstrap ROM resides at addresses BF00 BFFF and is only available when the MCU operates in special bootstrap operating mode Operating modes are determined by the logic levels applied to the MODB and MODA pins at reset In single chip mode the MCU functions as a self contained micro...

Page 19: ... not externally addressable z represents the val ue of bits EE 3 0 in the CONFIG register 5 EEPROM can be remapped to any 4 Kbyte boundary z000 z represents the value contained in EE 3 0 in the CONFIG register Figure 7 MC68HC11F1 Memory Map 0000 03FF 1000 105F FFC0 FFFF SINGLE CHIP MODA 0 MODB 1 EXPANDED MODA 1 MODB 1 SPECIAL TEST MODA 1 MODB 0 SPECIAL BOOTSTRAP MODA 0 MODB 0 BF00 BFFF EXTERNAL EX...

Page 20: ...Highest Priority Interrupt and Miscellaneous x03C Bit 7 6 5 4 3 2 1 Bit 0 RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1 PSEL0 RESET 0 0 0 0 0 1 0 1 Single Chip 0 0 1 0 0 1 0 1 Expanded 1 1 0 1 0 1 0 1 Bootstrap 0 1 1 1 0 1 0 1 Special Test 0000 03FF 1000 105F FFC0 FFFF SINGLE CHIP MODA 0 MODB 1 EXPANDED MODA 1 MODB 1 SPECIAL TEST MODA 1 MODB 0 SPECIAL BOOTSTRAP MODA 0 MODB 0 BF00 BFFF EXTERNAL EXTERNAL EXT...

Page 21: ...ect 0 Internal reads not visible 1 Data from internal reads is driven on the external data bus PSEL 3 0 See 5 2 Reset and Interrupt Registers page 27 The INIT register can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes NOTE The register diagram above applies to the MC68HC11FC0 only A diagram and bit descriptions of the INIT register in the MC68...

Page 22: ... Table 10 GWOM Port G Wired OR Mode Option Refer to 7 8 Parallel I O Registers page 36 INIT RAM and I O Mapping MC68HC11F1 only x03D Bit 7 6 5 4 3 2 1 Bit 0 RAM3 RAM2 RAM1 RAM0 REG3 REG4 REG1 REG0 RESET 0 0 0 0 0 0 0 1 Table 10 RAM and Register Mapping RAM 3 0 Location REG 3 0 Location 0000 0000 03FF 0000 0000 005F 0001 1000 13FF 0001 1000 105F 0010 2000 23FF 0010 2000 205F 0011 3000 33FF 0011 300...

Page 23: ...t This bit is implemented on the MC68HC11F1 only On the MC68HC11FC0 reads always return zero and writes have no effect 0 A D and EEPROM use system E clock 1 A D and EEPROM use internal RC clock IRQE IRQ Select Edge Sensitive Only 0 Low level recognition 1 Falling edge recognition DLY Enable Oscillator Start Up Delay on Exit from STOP 0 No stabilization delay on exit from STOP 1 Stabilization delay...

Page 24: ...it free running timer is divided into two 8 bit halves and the prescaler is bypassed The system E clock drives both halves directly DISR Disable Resets from COP and Clock Monitor In test and bootstrap modes this bit is reset to one to inhibit clock monitor and COP resets In normal modes DISR is reset to zero 0 Normal operation 1 COP and Clock Monitor failure do not generate a system reset FCM Forc...

Page 25: ...to the highest maskable priority position by writing to the HPRIO register This register can be written at any time provided the I bit in the CCR is set In addition to the global I bit all maskable interrupt sources except the external interrupt IRQ pin are subject to local enable bits in control registers Each of these interrupt sources also sets a correspond ing flag bit in a control register th...

Page 26: ...F FFDA DB Pulse Accumulator Input Edge I Bit PAII PAIF FFDC DD Pulse Accumulator Overflow I Bit PAOVI PAOVF FFDE DF Timer Overflow I Bit TOI TOF FFE0 E1 Timer Input Capture 4 Output Compare 5 I Bit I4 O5I I4 O5F FFE2 E3 Timer Output Compare 4 I Bit OC4I OC4F FFE4 E5 Timer Output Compare 3 I Bit OC3I OC3F FFE6 E7 Timer Output Compare 2 I Bit OC2I OC2F FFE8 E9 Timer Output Compare 1 I Bit OC1I OC1F ...

Page 27: ...1 0 11 1 MHz 0 32 768 ms 32 768 ms 131 072 ms 524 288 ms 2 097 s 2 MHz 0 16 384 ms 16 384 ms 65 536 ms 262 144 ms 1 049 s 3 MHz 0 10 923 ms 10 923 ms 43 691 ms 174 763 ms 699 051 ms 4 MHz 0 8 192 ms 8 192 ms 32 768 ms 131 072 ms 524 288 ms 5 MHz 0 6 554 ms 6 554 ms 26 214 ms 104 858 ms 419 430 ms 6 MHz 0 5 461 ms 5 461 ms 21 845 87 381 ms 349 525 ms Any E 0 215 E 215 E 217 E 219 E 221 E COPRST Arm...

Page 28: ...set on time out 1011 Timer Output Compare 1 1100 Timer Output Compare 2 1101 Timer Output Compare 3 1110 Timer Output Compare 4 1111 Timer Output Compare 5 Input Capture 4 CONFIG EEPROM Mapping COP EEPROM Enables x03F Bit 7 6 5 4 3 2 1 Bit 0 EE3 EE2 EE1 EE0 1 NOCOP 1 EEON RESET U U U U 1 U 1 U Table 13 Highest Priority Interrupt Selection Continued PSEL 3 0 Interrupt Source Promoted ...

Page 29: ...p charge pump develops the high voltage required for programming and erasing When the E clock frequency is 1 MHz or above the charge pump is driven by the E clock When the E clock fre quency is less than 1 MHz select the internal RC oscillator to drive the EEPROM charge pump by writ ing one to the CSEL bit in the OPTION register Refer to the discussion of the OPTION register in 4 3 System Initiali...

Page 30: ...able or disable EEPROM operation Bits in this register are user programmed except when forced to certain values as noted in the following bit descriptions EE 3 0 EEPROM Map Position EEPROM is located at xE00 xFFF where x is the value represented by these four bits In single chip and bootstrap modes EEPROM is forced to FE00 FFFF regardless of the state of these bits On factory fresh devices EE 3 0 ...

Page 31: ...0 ms 20 ms for low voltage operation 5 Clear the EEPGM bit in PPROG to turn off the high voltage 6 Clear the PPROG register to reconfigure EEPROM address and data buses for normal opera tions To program the EEPROM ensure that the proper bits of the BPROT register are cleared and then com plete the following steps 1 Write to PPROG with the EELAT bit set 2 Write data to the desired address 3 Write t...

Page 32: ... address of the byte to be erased BYTEE LDAB 16 BYTE 1 ROW 0 ERASE 1 EELAT 1 EEPGM 0 STAB 103B Set to BYTE erase mode STAB 0 X Store any data to address to be erased LDAB 17 BYTE 1 ROW 0 ERASE 1 EELAT 1 EEPGM 1 STAB 103B Turn on high voltage JSR DLY10 Delay 10 ms CLR 103B Turn off high voltage and set to READ mode 6 4 CONFIG Register Programming Because the CONFIG register is implemented with EEPR...

Page 33: ...es port B pins act as high order address lines ADDR 15 8 and accesses to PORTB the port B data register are mapped externally 7 3 Port C Port C is an eight bit general purpose I O port with a data register PORTC and a data direction register DDRC In single chip modes port C pins are general purpose I O pins PC 7 0 Port C can be config ured for wired OR operation in single chip modes by setting the...

Page 34: ...that is indeterminate The contents of the corresponding latches are dependent upon the electrical state of the pins during reset In port descrip tions an I indicates this condition Port pins that are driven to a known logic level during reset are shown with a value of either one or zero Some control bits are unaffected by reset Reset states for these bits are indicated with a U I Indeterminate val...

Page 35: ...re high impedance inputs In expanded or test modes port C pins are data bus inputs outputs and PORTC is not in the memory map The R W signal is used to control the direction of data transfers For DDRx bits 0 input and 1 output DDRG Port G Data Direction Register x003 Bit 7 6 5 4 3 2 1 Bit 0 DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 RESET 0 0 0 0 0 0 0 0 PORTB Port B Data Register x004 Bit 7 6 5 4 3 ...

Page 36: ...gital converter The A D converter is not present on the MC68HC11FC0 GWOM Port G Wired OR Mode Option This bit affects all port G pins together 0 Port G outputs are normal CMOS outputs 1 Port G outputs act as open drain outputs NOTES 1 These bits are not present on the MC68HC11FC0 and will always read zero 2 This bit is not present on the 64 pin QFP version of the MC68HC11FC0 and will always read z...

Page 37: ...MOS outputs 1 Port C outputs act as open drain outputs CLK4X 4XCLK Output Enable Refer to 4 3 System Initialization Registers page 23 LIRDV Load Instruction Register Driven Refer to 4 3 System Initialization Registers page 23 Bits 3 1 0 Not implemented Reads always return zero and writes have no effect SPRBYP Refer to 10 2 SPI Registers page 52 ...

Page 38: ... flexible of the four chip selects Polarity valid assertion time and block size are determined by the GNPOL GAVLD GSIZA GSIZB and GSIZC bits of the CSGSIZ register The starting address is selected with the CSGADR register Each of the four chip selects has two associated bits in the chip select clock stretch register CSSTRH These bits allow clock stretching from zero to three cycles full E clock pe...

Page 39: ...select 1 General purpose chip select has priority over program chip select Refer to Table 17 NOTES 1 EEPROM is present on the MC68HC11F1 only Table 16 Chip Select Clock Stretch Control Clock Stretch Bits A B Clock Stretch 0 0 0 Cycles 0 1 1 Cycle 1 0 2 Cycles 1 1 3 Cycles CSCTL Chip Select Control x05D Bit 7 6 5 4 3 2 1 Bit 0 IO1EN IO1PL IO2EN IO2PL GCSPR PCSEN PSIZA PSIZB RESET 0 0 0 0 0 0 0 Tabl...

Page 40: ...time E clock high 1 CSIO1 is valid during address valid time IO2AV I O Chip Select 2 Address Valid 0 CSIO2 is valid during E clock valid time E clock high 1 CSIO2 is valid during address valid time Table 18 Program Chip Select Size Control PSIZA PSIZB Size Address Range 0 0 64 Kbytes 0000 FFFF 0 1 32 Kbytes 8000 FFFF 1 0 16 Kbytes C000 FFFF 1 1 8 Kbytes E000 FFFF CSGADR General Purpose Chip Select...

Page 41: ...igh GAVLD General Purpose Chip Select Address Valid 0 CSGEN is valid during E clock valid time E clock high 1 CSGEN is valid during address valid time GSIZ A C Block Size for CSGEN Refer to Table 20 for bit values Table 20 General Purpose Chip Select Size Control GSIZ A C Address Size 000 64 Kbytes 001 32 Kbytes 010 16 Kbytes 011 8 Kbytes 100 4 Kbytes 101 2 Kbytes 110 1 Kbyte 111 0 Kbytes disabled...

Page 42: ...er and receiver are independent but use the same data for mat and bit rate 9 1 SCI Block Diagrams Figure 9 SCI Transmitter Block Diagram TC TDRE SCSR1 SCI STATUS 1 SCCR2 SCI CONTROL 2 TRANSMITTER CONTROL LOGIC TCIE TC TIE TDRE SCI Rx QUESTS SCI INTERRUPT REQUEST INTERNAL DATA BUS PIN BUFFER AND CONTROL H 10 11 BIT Tx SHIFT REGISTER DDD1 SCDR Tx BUFFER TRANSFER Tx BUFFER SHIFT ENABLE JAM ENABLE PRE...

Page 43: ...EQUEST INTERNAL DATA BUS H 10 11 BIT M SCCR1 SCI CONTROL 1 RECEIVER BAUD RATE CLOCK RIE ILIE 8 7 6 5 4 3 2 1 0 L PD0 RxD SCDR Rx BUFFER Rx SHIFT REGISTER DDD0 PIN BUFFER AND CONTROL DATA RECOVERY 16 STOP START MSB ALL ONES RE WAKEUP LOGIC RDRF IDLE OR NF FE RWU DISABLE DRIVER WAKE READ ONLY RDRF RIE IDLE ILIE OR RIE R8 T8 TDRE RE TC TIE TCIE TE SBK ...

Page 44: ...ress NOTES 1 A blank table cell indicates that an uncommon rate results BAUD Baud Rate x02B Bit 7 6 5 4 3 2 1 Bit 0 TCLR SCP2 SCP1 SCP0 RCKB SCR2 SCR1 SCR0 RESET 0 0 0 0 0 U U U Table 21 Baud Rate Prescaler Selection SCP 2 0 Divide Internal Clock By Prescaler Output1 XTAL 4 0 MHz XTAL 4 9152 MHz XTAL 8 0 MHz XTAL 10 0 MHz XTAL 12 0 MHz XTAL 16 0 MHz XTAL 20 0 MHz XTAL 24 0 MHz X00 1 62500 76800 12...

Page 45: ...de by two stages to arrive at the receiver timing RT clock rate The baud rate clock is the result of dividing the RT clock by 16 Figure 11 SCI Baud Rate Generator Block Diagram OSCILLATOR AND CLOCK GENERATOR 4 XTAL EXTAL E INTERNAL BUS CLOCK PH2 SCR 2 0 3 X00 001 4 X10 13 X11 0 0 0 2 0 0 1 2 0 1 0 2 0 1 1 2 1 0 1 2 1 0 0 2 1 1 1 2 1 1 0 16 SCI Receive Baud Rate 16x SCI Transmit Baud Rate 1x 9 101 ...

Page 46: ...d 1 SCI interrupt requested when the TDRE flag is set TCIE Transmit Complete Interrupt Enable 0 TC interrupts disabled 1 SCI interrupt requested when the TC flag is set RIE Receiver Interrupt Enable 0 RDRF and OR interrupts disabled 1 SCI interrupt requested when the RDRF flag or the OR flag is set ILIE Idle Line Interrupt Enable 0 IDLE interrupts disabled 1 SCI interrupt requested when IDLE statu...

Page 47: ...pty 1 SCDR full IDLE Idle Line Detected Flag This flag is set if the RxD line is idle Once cleared IDLE is not set again until the RxD line has been active and becomes idle again The IDLE flag is inhibited when RWU 1 Clear IDLE by reading SCSR with IDLE set and then reading SCDR 0 RxD line is active 1 RxD line is idle OR Overrun Error Flag OR is set if a new character is received before a previous...

Page 48: ... no effect I Indeterminate value Reading SCDR retrieves the last byte received in the receive data buffer Writing to SCDR loads the transmit data buffer with the next byte to be transmitted SCDR Serial Communications Data Register x02F Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 2 Bit 0 RESET I I I I I I I I ...

Page 49: ...d as slave The MC68HC11FC0 has an additional control bit that allows the SPI baud rate counter to be bypassed This allows a master mode baud rate equal to the E clock frequency 10 1 SPI Block Diagram Figure 12 SPI Block Diagram SYSTEM CONFIGURATION OPTION 2 REGISTER INTERNAL MCU CLOCK 2 4 16 32 DIVIDER SELECT SPRBYP SPI CONTROL REGISTER SPIE SPE DWOM MSTR CPHA DOTTED LINE CONNECTIONS 8 BIT SHIFT R...

Page 50: ...SPI Pins PD 5 2 0 Normal CMOS outputs 1 Open drain outputs MSTR Master Mode Select 0 Slave mode 1 Master mode CPOL Clock Polarity When the clock polarity bit is cleared and data is not being transferred the SCK pin of the master device has a steady state low value When CPOL is set SCK idles high Refer to Figure 13 CPHA Clock Phase The clock phase bit in conjunction with the CPOL bit controls the c...

Page 51: ...write collision 1 Write collision Bit 5 Not Implemented Reads always return zero and writes have no effect MODF Mode Fault A mode fault terminates SPI operation Set when SS is pulled low while MSTR 1 MODF is cleared by reading SPSR read with MODF set followed by a write to SPCR 0 No mode fault 1 Mode fault Bits 3 0 Not Implemented Reads always return zero and writes have no effect Incoming SPI dat...

Page 52: ...ypass 0 Enable SPI baud rate counter 1 Bypass SPI baud rate counter When the SPI baud rate counter is bypassed the SPI can transmit at a maximum master mode baud rate equal to the E clock frequency SPRBYP is present only on the MC68HC11FC0 and overrides the setting of SPR 1 0 in SPCR OPT2 System Configuration Option Register 2 x038 Bit 7 6 5 4 3 2 1 Bit 0 GWOM CWOM CLK4X LIRDV SPRBYP RESET 0 0 1 0...

Page 53: ...ems operating at clock rates of 750 kHz or below must use an internal RC oscillator The CSEL bit in the OPTION register se lects the clock source for the A D system The CSEL bit is described in 11 3 A D Registers page 56 A multiplexer allows the single A D converter to select one of 16 analog signals as shown in Table 24 NOTE The A D converter is present on the MC68HC11F1 only Figure 14 A D Conver...

Page 54: ...y or stop after one iteration The conversion complete flag CCF is set after the fourth conversion in a sequence to show the availability of data in the result registers Figure 16 shows the timing of a typical sequence Synchronization is referenced to the system E clock Figure 16 A D Conversion Sequence DIFFUSION POLY 2 pF COUPLER 400 nA JUNCTION LEAKAGE 20V 0 7V THIS ANALOG SWITCH IS CLOSED ONLY D...

Page 55: ...ple Channel Single Channel Control 0 Convert single channel selected 1 Convert four channels in selected group CD CA Channel Select D through A Refer to Table 24 When a multiple channel mode is selected MULT 1 the two least significant chan nel select bits CB and CA have no meaning and the CD and CC bits specify which group of four chan nels is to be converted NOTES 1 Used for factory testing ADCT...

Page 56: ...r Up 0 A D powered down 1 A D powered up CSEL Clock Select 0 A D and EEPROM use system E Clock 1 A D and EEPROM use internal RC clock Bits 5 0 Refer to 4 3 System Initialization Registers page 23 NOTES 1 of VRH VRL 2 Volts for VRL 0 VRH 5 0 V ADR1 ADR4 A D Results x031 x034 x031 Bit 7 6 5 4 3 2 1 Bit 0 ADR1 x032 Bit 7 6 5 4 3 2 1 Bit 0 ADR2 x033 Bit 7 6 5 4 3 2 1 Bit 0 ADR3 x034 Bit 7 6 5 4 3 2 1 ...

Page 57: ...4 288 ms 3 MHz 0 333 µs 21 845 ms 1 333 µs 87 381 ms 2 667 µs 174 763 ms 5 333 µs 349 525 ms 4 MHz 0 250 µs 16 384 ms 1 000 µs 65 536 ms 2 000 µs 131 072 ms 4 000 µs 262 144 ms 5 MHz 0 200 µs 13 107 ms 0 800 µs 52 429 ms 1 600 µs 104 858 ms 3 200 µs 209 715 ms 6 MHz 0 167 µs 10 923 ms 0 667 µs 43 691 ms 1 333 µs 87 381 ms 2 667 µs 174 763 ms Any E 1 E 216 E 4 E 218 E 8 E 219 E 16 E 220 E Table 27 ...

Page 58: ...OC3I OC4I I4O5I 7 6 5 4 FOC2 FOC3 FOC4 FOC5 16 BIT COMPARATOR TOC2 LO TOC2 HI 16 BIT COMPARATOR TOC3 LO TOC3 HI 16 BIT COMPARATOR TOC4 LO TOC4 HI 16 BIT COMPARATOR TI4O5 LO TI4O5 HI 3 2 1 IC1I IC2I IC3I OC1I OC2I OC2F OC3F OC4F I4O5F IC1F TIC1 LO TIC1 HI IC2F IC3F TIC2 LO TIC2 HI TIC3 LO TIC3 HI 9 PRESCALER Divide by 1 4 8 or 16 Interrupt Requests Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Co...

Page 59: ...s 2 0 Not implemented Reads always return zero and writes have no effect The 16 bit read only TCNT register contains the prescaled value of the 16 bit timer A full counter read addresses the most significant byte MSB first A read of this address causes the least significant byte to be latched into a buffer for the next CPU cycle so that a double byte read returns the full 16 bit state of the count...

Page 60: ...ow x012 Bit 15 14 13 12 11 10 9 Bit 8 High x013 Bit 7 6 5 4 3 2 1 Bit 0 Low x014 Bit 15 14 13 12 11 10 9 Bit 8 High x015 Bit 7 6 5 4 3 2 1 Bit 0 Low TOC1 TOC4 Timer Output Compare x016 x01D x016 Bit 15 14 13 12 11 10 9 Bit 8 High x017 Bit 7 6 5 4 3 2 1 Bit 0 Low x018 Bit 15 14 13 12 11 10 9 Bit 8 High x019 Bit 7 6 5 4 3 2 1 Bit 0 Low x01A Bit 15 14 13 12 11 10 9 Bit 8 High x01B Bit 7 6 5 4 3 2 1 B...

Page 61: ...le bit ICxI Input Capture x Interrupt Enable If the ICxI enable bit is set when the ICxF flag bit is set a hardware interrupt sequence is requested Bits in TFLG1 are cleared by writing a one to the corresponding bit positions Table 29 Output Compare Actions OMx OLx Action Taken on Successful Compare 0 0 Timer disconnected from output pin logic 0 1 Toggle OCx output line 1 0 Clear OCx output line t...

Page 62: ...et Bits 5 4 See 13 2 Pulse Accumulator Registers page 64 Bits 3 2 Not implemented Reads always return zero and writes have no effect PR 1 0 Timer Prescaler Select Determines the main timer prescale factor as shown in Table 31 See Table 26 for specific frequencies Bits in this register indicate when certain timer system events have occurred Coupled with the four high order bits of TMSK2 the bits of...

Page 63: ...r for IC or OC 0 OC5 function enabled 1 IC4 function enabled RTR 1 0 RTI Interrupt Rate Selects These two bits select one of four rates for the real time interrupt circuit as shown in Table 32 PACTL Pulse Accumulator Control x026 Bit 7 6 5 4 3 2 1 Bit 0 0 PAEN PAMOD PEDGE 0 I4 O5 RTR1 RTR0 RESET 0 0 0 0 0 0 0 0 Table 32 Real Time Interrupt Periods E Clock Frequency RTR 1 0 00 RTR 1 0 01 RTR 1 0 10...

Page 64: ...remains at a predetermined logic level 13 1 Pulse Accumulator Block Diagram Figure 18 Pulse Accumulator Block Diagram 13 2 Pulse Accumulator Registers Bits 7 4 in TMSK2 correspond bit for bit with flag bits in TFLG2 Setting any of these bits enables the corresponding interrupt source TMSK2 Timer Interrupt Mask 2 x024 Bit 7 6 5 4 3 2 1 Bit 0 TOI RTII PAOVI PAII 0 0 PR1 PR0 RESET 0 0 0 0 0 0 0 0 PAC...

Page 65: ...w Flag Set when PACNT rolls over from FF to 00 PAIF Pulse Accumulator Input Edge Flag Set each time a selected active edge is detected on the PAI input line Bits 3 0 Not implemented Reads always return zero and writes have no effect Bit 7 Not implemented Reads always return zero and writes have no effect PAEN Pulse Accumulator System Enable 0 Pulse accumulator disabled 1 Pulse accumulator enabled ...

Page 66: ...gated time accumulation mode The counter is not affected by reset and can be read or written at any time Counting is synchronized to the internal PH2 clock so that incrementing and reading occur during opposite half cycles Table 33 Pulse Accumulator Edge Control PAMOD PEDGE Action on Clock 0 0 PAI falling edge increments the counter 0 1 PAI rising edge increments the counter 1 0 A zero on PAI inhi...

Page 67: ...MC68HC11F1 FC0 MOTOROLA MC68HC11FTS D 67 ...

Page 68: ...ations All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sus...

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