Motorola SE4710, Integration Manual, Page: 64 / 82

6 - 2 SE4710 Integration Guide
Output Data Timing
Data output is synchronized with the PIXCLK output. When LINE_VALID is high, one 8-bit pixel datum is output
every PIXCLK period.
Figure 6-2
Row Timing and FRAME_VALID / LINE_VALID Signals
Figure 6-3
Pixel Data Timing Example
Table 6-1
Frame Time @ 42 MHz
Parameter Description Pixel Clock Time Units
A Active data time 1280 30.48 µs
With stats enabled 1360 32.38 µs
P1 Frame start blanking 18 0.43 µs
P2 Frame end blanking 14 0.33 µs
Q Horizontal blanking 408 9.71 µs
With stats enabled 328 7.81 µs
A + Q Row time 1688 40.19 µs
V
Vertical blanking 47,638 1.13 ms
With stats enabled 47,558 1.13 ms
Nrows
Frame 1,350,024 32.14 ms
With stats enabled 1,350,104 32.15 ms
F Total 1,397,662 33.28 ms
. . .
. . .
. . .
FRAME_VALID
LINE_VALID
Number of Pixel Clocks P1 A Q A Q A P2
LINE_VALID
PIX CLK
D
OUT (7:0)
. . . .
. . . .
. . . .
. . . .
P0 P1 P P3 P4 Pn-1 Pn
Valid Image Data
Blanking Blanking
2