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MVME3100 Programmer’s Guide (V3100A/PG1)

Chapter 2 Programming Details

30

Notes

1.

Each SPD defines the physical attributes of each bank or group of banks. If both banks of a
SODIMM are populated, they are the same speed and memory size.

2.

This is a dual address serial EEPROM.

3.

The device address is user selectable using switches on the RTM. The recommended address
setting for the MVME3100 is $AA.

User Configuration EEPROM

The MVME3100 board provides two 64KB dual address serial EEPROMs for a total of 128KB user
configuration storage. These EEPROMs are hardwired to have device IDs as shown in

Table 2-4 on

page 29

, and each device ID will not be used for any other function. Refer to the

2-Wire Serial EEPROM

Datasheet

listed in

Appendix A,

Related Documentation

, for additional details.

VPD EEPROM

The MVME3100 board provides an 8KB dual address serial EEPROM containing vital product data
(VPD) configuration information specific to the MVME3100. Typical information that may be present in
the EEPROM may include: manufacturer, board revision, build version, date of assembly, memory
present, options present, L2 cache information, etc. The VPD EEPROM is hardwired to have a device
ID as shown in

Table 2-4 on page 29

. Refer to the

2-Wire Serial EEPROM Datasheet

listed in

Appendix

A,

Related Documentation

, for additional details.

$A8

100

8192 x 8

VPD (on-board system
configuration)

2

$AA

101

8192 x 8

RTM VPD (off-board configuration)

2, 3

$AC

110

Reserved

$AE

111

Reserved

$D0

N/A

N/A

DS1375 real-time clock

Table 2-4. I2C Bus Device Addressing (continued)

I2C Bus
Address

Device Address
A2 A1 A0
(binary)

Size (bytes)

Device Function

Notes

«
...
40
41
42
43
44
...
»

Summary of Contents for MVME3100

Page 1: ...MVME3100 Single Board Computer Programmer s Guide V3100A PG1 March 2006 Edition ...

Page 2: ...ted in the United States of America Motorola and the stylized M logo are trademarks of Motorola Inc registered in the U S Patent and Trademark Office All other product or service names mentioned in this document are the property of their respective owners ...

Page 3: ...the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power ...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Caution Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constr...

Page 5: ...ods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class A EN55024 Information technology equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintai...

Page 6: ...sible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contain...

Page 7: ...gister 11 Flash Control Status Register 12 PCI Bus Status Registers 13 Interrupt Detect Register 16 Presence Detect Register 17 PLD Revision Register 18 PLD Data Code Register 18 Test Register 1 19 Test Register 2 19 External Timer Registers 19 Prescalar Register 20 Control Registers 20 Compare Registers 21 Counter Registers 22 Geographical Address Register 22 2 Programming Details 23 Introduction...

Page 8: ...t PHY Address 31 Flash Memory 31 PCI IDSEL Definition 32 PCI Arbitration Assignments 34 Clock Distribution 34 MPC8540 Real Time Clock Input 36 MPC8540 LBC Clock Divisor 36 Motorola Computer Group Documents 37 Manufacturers Documents 38 Related Specifications 40 ...

Page 9: ...MVME3100 Programmer s Guide V3100A PG1 ix Figure 1 1 MVME3100 Block Diagram 2 List of Figures ...

Page 10: ... Table 1 16 PLD Data Code Register 18 Table 1 17 Test Register 1 19 Table 1 18 Test Register 2 19 Table 1 19 Prescalar Register 20 Table 1 20 Tick Timer Control Registers 20 Table 1 21 Tick Timer Compare Registers 22 Table 1 22 Tick Timer Counter Registers 22 Table 2 1 MPC8540 Power on Reset Configuration Settings 24 Table 2 2 MPC8540 Interrupt Controller 28 Table 2 3 LBC Chip Select Assignments 2...

Page 11: ...ing IDSEL mapping interrupt assignments for the MPC8540 interrupt controller Flash memory two wire serial interface addressing and other device and system considerations Appendix A Related Documentation provides a listing of related Motorola manuals vendor documentation and industry specifications Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want...

Page 12: ... this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values for function parameters and for structure names and fields Italic is also used for comments in screen displays and examples and to introduce new terms c...

Page 13: ...y map system I O memory map and other configuration registers Overview The MVME3100 is a single slot single board computer based on the MPC8540 PowerQUICC III integrated processor The MVME3100 provides serial ATA sATA USB 2 0 2eSST VMEbus interfaces dual 64 bit 100 MHz PMC sites up to 256MB of Flash dual 10 100 1000 Ethernet one 10 100 Ethernet and five serial ports This board supports front and r...

Page 14: ...emory User 128KB RTC DS1375 VPD 8KB VME TSI148 XCVR 22501 XCVR RS232 CPLD Decode Timers Regs RTC DS1621 Quart 16C554 sATA GD31244 USB uPD720101 Flash 128MB Clock Distribution Reset Control Power Supplies P2P PCI6520 P2P PCI6520 PMCSpan Planar Connector Bus A PCI X 66MHz PMC 1 PMC 2 sATA 1 VME Bus I2C Bus USB 2 PMC 1 Jn4 IO COM2 COM5 10 100 sATA 2 USB 2 USB 1 GigE 2 Bus C PCI 33 MHz Bus B PCI X 66 ...

Page 15: ...oot sectors selectable via a hardware switch Hardware switch or software bit write protection for entire logical bank PCI Interface Bus A 66 MHz PCI X PCI X 1 0b compliant One TSi148 VMEbus controller One serial ATA sATA controller Two PCI6520 PCI X to PCI X bridges primary side Bus B 33 66 100 MHz PCI PCI X PCI 2 2 and PCI X 1 0b compliant Two 3 3V 5V selectable VIO 64 bit single wide PMC sites o...

Page 16: ... 16550 compatible 9 6 to 115 2 KBAUD asynchronous serial channels for rear P2 I O Timers Four 32 bit MPC8540 timers Four 32 bit timers in a PLD Watchdog Timer One MPC8540 watchdog timer VME Interface VME64 ANSI VITA 1 1994 compliant VME64 Extensions ANSI VITA 1 1 1997 compliant 2eSST ANSI VITA 1 5 2003 compliant VITA 41 0 version 0 9 compliant Two five row P1 and P2 backplane connectors One TSi148...

Page 17: ...fault location for the CCSRs but it is not mapped after reset 2 Only FFFF F000 to FFFF FFFF is mapped after reset The e500 core fetches the first instruction from FFFF FFFC following a reset Table 1 2 MVME712 101 RTM Features Summary Feature Description I O One five row P2 backplane connector for serial and Ethernet I O passed from the MVME3100 Four RJ 45 connectors for rear panel I O four asynchr...

Page 18: ...p The MVME3100 is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2GB Table 1 4 MOTLoad s Processor Address Map Processor Address Size Definition Notes Start End 0000 0000 top_dram 1 dram_size 2GB max System Memory on board DRAM 8000 0000 DFFF FFFF 1 5GB PCI Memory Space VME E000 0000 E0FF FFFF 16MB PCI I O Space E100 0000 E10F FFFF 1MB MPC85...

Page 19: ...05 PCI Bus B Status Register 2 3 E200 0006 PCI Bus C Status Register 2 3 E200 0007 Interrupt Detect Register 2 3 E200 0008 Presence Detect Register 2 3 E200 0009 PLD Revision 2 3 E200 000C PLD Date Code 32 bits 2 3 E200 0010 Test Register 1 32 bits 2 3 E200 0014 Test Register 2 32 bits 2 3 E200 0018 E200 0FFF Reserved 1 E201 1000 E201 1FFF COM 2 QUART channel 1 3 E201 2000 E201 2FFF COM 3 QUART ch...

Page 20: ...rnal PLD Tick Timer 3 Control Register 4 2 E202 0034 External PLD Tick Timer 3 Compare Register 4 2 E202 0038 External PLD Tick Timer 3 Counter Register 4 2 E202 003C Reserved 4 2 E202 0040 External PLD Tick Timer 4 Control Register 4 2 E202 0044 External PLD Tick Timer 4 Compare Register 4 2 E202 0048 External PLD Tick Timer 4 Counter Register 4 2 E202 004C E2FF FFFF Reserved 1 Table 1 5 System I...

Page 21: ...determine the state of the abort switch A cleared condition indicates the abort switch is not depressed while a set condition indicates the abort switch is asserted SAFE_START ENV safe start This bit reflects the current state of the ENV safe start select switch A set condition indicates that firmware should use the safe ENV settings A cleared condition indicates that the ENV settings programmed i...

Page 22: ...Clearing this bit will enable writes to the EEPROM devices Setting this bit write protects the devices The devices are write protected following a reset BRD_RST Board reset These bits force a hard reset of the board If a pattern is written in bits 5 7 where bit 7 is set bit 6 is cleared and bit 5 is set 101 a hard reset is generated Any other pattern written in bits 5 7 does not generate a hard re...

Page 23: ...the front panel LED USR1_LED User LED 1 This bit controls the USR1 LED located on the front panel A set condition illuminates the front panel LED and a cleared condition extinguishes the front panel LED USR2_LED User LED 2 This bit controls the planar USR2 LED A set condition illuminates the LED and a cleared condition extinguishes the LED USR3_LED User LED 3 This bit controls the planar USR3 LED ...

Page 24: ...ch A set condition indicates that the entire Flash bank is write protected A cleared condition indicates that the Flash bank is not write protected F_WP_SW Software Flash bank write protect This bit provides software controlled protection against inadvertent writes to the Flash memory devices A set condition indicates that the entire Flash is write protected A cleared condition indicates that the ...

Page 25: ...133 MHz PCIX_A PCI X bus A A set condition indicates that bus A is operating in PCI X mode A cleared condition indicates PCI mode PCI_A_64B PCI bus A 64 bit A set condition indicates that bus A is enabled to operate in 64 bit mode A cleared condition indicates 32 bit mode RSVD Reserved for future implementation Table 1 10 PCI Bus A Status Register REG PCI Bus A Status Register 0xE2000004 BIT 7 6 5...

Page 26: ...numeration when set If cleared the PrPMC module is not ready for enumeration If no PrPMC is installed this bit is always set ERDY2 EREADY2 Indicates that the PrPMC module installed in PMC site 2 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration If no PrPMC is installed the bit is always set 5 0V_VIO 5 0V VIO Enabled This bit set indicates that the PMC bus P...

Page 27: ... C is operating in PCI X mode A cleared condition indicates PCI mode PCI_C_64B PCI bus C 64 bit A set condition indicates that bus C is enabled to operate in 64 bit mode A cleared condition indicates 32 bit mode RSVD Reserved for future implementation Table 1 12 PCI Bus C Status Register REG PCI Bus C Status Register 0xE2000006 BIT 7 6 5 4 3 2 1 0 FIELD RSVD RSVD RSVD RSVD PCI_C_64B PCIX_C PCI_C_S...

Page 28: ...EC1 interrupt is not asserted If set the TSEC1 interrupt is asserted TSEC2_PHY TSEC2 PHY interrupt If cleared the TSEC2 interrupt is not asserted If set the TSEC2 interrupt is asserted FEC_PHY FEC PHY interrupt If cleared the FEC interrupt is not asserted If set the FEC interrupt is asserted RSVD Reserved for future implementation Table 1 13 Interrupt Detect Register REG Interrupt Detect Register ...

Page 29: ...le installed in site 1 If set the PMC module is installed PMC2P PMC module 2 present If cleared there is no PMC module installed in site 2 If set the PMC module is installed PEP PMCspan present If cleared there is no PMCspan module installed If set the PMCspan module is installed RSVD Reserved for future implementation Table 1 14 Presence Detect Register REG Presence Detect Register 0xE2000008 BIT...

Page 30: ...mer register PLD revision The revision number starts with 01 PLD Data Code Register The MVME3100 PLD provides a 32 bit register that contains the build date code of the timers registers PLD yy Last two digits of the year mm Month dd Day vv Version Table 1 15 PLD Revision Register REG PLD Revision Register 0xE2000009 BIT 7 6 5 4 3 2 1 0 FIELD PLD_REV OPER R RESET 01 Table 1 16 PLD Data Code Registe...

Page 31: ...address returns the complement of the data pattern in test register 1 A write to this address writes the uncomplemented data to register TEST1 External Timer Registers The MVME3100 provides a set of tick timer registers for access to the four external timers implemented in the timers registers PLD These registers are 32 bit registers and are not byte writable The following sections describe the ex...

Page 32: ...ed by each of the four timers The tick timers require a 1 MHz clock input The input clock to the prescaler is 25 MHz The default value is set for E7 which gives a 1 MHz reference clock for a 25 MHz input clock source ENC Enable counter When this bit is high the counter increments When this bit is low the counter does not increment Table 1 19 Prescalar Register REG Prescalar Register 0xE2020000 8 b...

Page 33: ...pt to the local bus interrupter The overflow counter can be cleared by writing a 1 to the COVF bit ENINT Enable interrupt When this bit is high the interrupt is enabled When this bit is low the interrupt is not enabled CINT Clear interrupt INTS Interrupt status RSVD Reserved for future implementation Compare Registers The tick timer counter is compared to the Compare register When they are equal t...

Page 34: ...the TSi148 provides the VMEbus geographical address of the MVME3100 This register reflects the inverted states of the geographical address pins at the 5 row 160 pin P1 connector Table 1 21 Tick Timer Compare Registers REG Tick Timer 1 Compare Register 0xE202 0014 32 bits Tick Timer 2 Compare Register 0xE202 0024 32 bits Tick Timer 3 Compare Register 0xE202 0034 32 bits Tick Timer 4 Compare Registe...

Page 35: ...0 Interrupt Controller on page 28 Local Bus Controller Chip Select Assignments on page 29 Two Wire Serial Interface on page 29 User Configuration EEPROM on page 30 VPD EEPROM on page 30 RTM VPD EEPROM on page 31 Ethernet PHY Address on page 31 Flash Memory on page 31 PCI IDSEL Definition on page 32 PCI Arbitration Assignments on page 34 Clock Distribution on page 34 MPC8540 Real Time Clock Input o...

Page 36: ... Setting Description State of Bit vs Function 1 PCI_REQ64_L PLD logic 0 PCI 32 Configuration 0 PCI PCI X interface is 64 bit 1 PCI PCI X interface is 32 bit PCI_GNT1_L Resistor 0 PCI Interface I O Impedance 0 25 ohm drivers 1 42 ohm drivers PCI_GNT2_L Resistor 1 PCI Arbiter Configuration 0 Disabled on chip PCI PCI X arbiter 2 1 Enabled on chip PCI PCI X arbiter PCI_GNT3_L Resistor 1 PCI Debug Conf...

Page 37: ...de TSEC2_ TXD 6 5 Resistors 11 Local Bus Output Hold Configuration 00 0 added buffer delays 0 added buffer delays for LALE 01 3 added buffer delays 1 added buffer delay for LALE 10 2 added buffer delays 1 added buffer delay for LALE 11 1 added buffer delay 0 added buffer delays for LALE TSEC2_ TXD 2 4 Fixed 000 RapidIO Device ID 3 lower order bits 000 Unconnected Inputs LA27 Resistor 1 CPU Boot Co...

Page 38: ... added buffer delays 10 1 added buffer delay 11 0 added buffer delays6 LWE 2 3 _L Resistors 11 MPC8540 Host Agent Configuration 00 Agent of RapidIO and PCI PCI X 01 Agent of a RapidIO 10 Agent of a PCI PCI X 11 Host of both RapidIO and PCI PCI X LALE LGPL2 Resistor 01 e500 Core Clock PLL Ratio e500 Core CCB Clock 00 2 1 01 5 2 10 3 1 11 7 2 LGPL0 LGPL1 Fixed 11 RapidIO Transmit Clock Source 00 Res...

Page 39: ... LGPL5 Fixed 11 Boot Sequencer Configuration 00 Reserved 01 Boot sequencer enabled with normal I2C address mode 10 Boot sequencer enabled with extended I2C address mode 11 Boot sequencer disabled LAD 28 31 Resistor 7 XX General Purpose POR Configuration XX General purposePOR configuration vector to be placed in CPPORCR register bits MSRCID0 Resistor 1 Memory Debug Configuration 0 Debug info from t...

Page 40: ...xternal timers are implemented in a PLD 2 External UARTs are implemented using a QUART Refer to the MPC8540 Reference Manual listed in Appendix A Related Documentation for additional details regarding the operation of the MPC8540 PIC Table 2 2 MPC8540 Interrupt Controller Interrupt Edge Level Polarity Interrupt Source Notes 0 Level Low VME0 1 Level Low VME1 External Timers 1 2 Level Low VME2 sATA ...

Page 41: ...tents of the various I2 C devices located on the MVME3100 The following table contains the I2 C devices used for the MVME3100 and their assigned device addresses Table 2 3 LBC Chip Select Assignments LBC Bank Chip Select Local Bus Function Size Data Bus Width Notes 0 Boot Flash bank 32MB 128MB 32 bits 1 1 Optional second Flash bank 32MB 128MB 32 bits 1 2 Control Status registers 64 KB 32 bits 2 3 ...

Page 42: ...M Datasheet listed in Appendix A Related Documentation for additional details VPD EEPROM The MVME3100 board provides an 8KB dual address serial EEPROM containing vital product data VPD configuration information specific to the MVME3100 Typical information that may be present in the EEPROM may include manufacturer board revision build version date of assembly memory present options present L2 cache...

Page 43: ...operate in 16 bit mode to form a 32 bit Flash bank The Flash bank connected to LBC Chip Select 0 is the boot bank and is always populated The second Flash bank connected to LBC Chip Select 1 may or may not be populated depending on Flash size requirements and available Flash devices The VPD Flash packet s will determine which banks are populated and the size of the devices Software must program on...

Page 44: ...ck switch is used to select between boot block A and boot block B When the switch is OFF the Flash memory map is normal and block A is selected When the switch is ON block B is mapped to the highest address as shown below The MAP_SEL bit in the Flash Control Status register can override the switch and restore the memory map to the normal configuration with block A selected Upon RESET this mapping ...

Page 45: ...on PMCSpan PCI Expansion 21150 0b0_0010 18 PMCSpan Slot 1 IRQ6 IRQ7 IRQ4 IRQ5 0b0_0011 19 PMCSpan Slot 2 IRQ7 IRQ4 IRQ5 IRQ6 0b0_0100 20 PMCSpan Slot 3 IRQ4 IRQ5 IRQ6 IRQ7 0b0_0101 21 PMCSpan Slot 4 IRQ5 IRQ6 IRQ7 IRQ4 Table 2 8 Planar PCI Device Identification Function Device Vendor ID Device ID System Controller MPC8540 0x1057 0x0008 PCI X to PCI X Bridge PCI6520CB 0x10B5 0x6520 VME Controller T...

Page 46: ...ge jitter and low clock to clock skew required by the devices Additional clocks required by individual devices are generated near the devices using individual oscillators Table 2 10 on page 35 lists the clocks required on the MVME3100 along with their frequency and source The clock tree A frequencies on bus A have a default configuration of 66 MHz The 33 66 100 MHz clocks are dynamically configure...

Page 47: ...V PMC2 CLK_PMC2 33 66 100 B 1 3 3V PCI6520 Secondary CLK_P2P_ABS 33 66 100 B 1 3 3V CLK_P2P_ACS 33 C 1 3 3V USB CLK_USB 33 C 1 3 3V PMCspan CLK_SPAN 33 C 1 3 3V MPC9855 CLK66 25 Oscillator 2 3 3V BCM5461S CLK25_25V_PHY 25 Oscillator Buffer 2 2 5V BCM5221 CLK25_33V_PHY 25 Oscillator Buffer 1 3 3V Control and Timers PLD CLK25_33V_PLD 25 Oscillator Buffer 1 3 3V CLK_LBC CCB_CLK 8 333 MHz 8 MPC8540 1 ...

Page 48: ...lock as the RTC timer reference software must set the SEL_TBCLK bit in the MPC8540 HID0 register MPC8540 LBC Clock Divisor The MPC8540 LBC clock output is used by the control and timers PLD The LBC clock is derived from a divide by 2 4 or 8 ratio of the internal CCB core complex bus clock as determined by the clock ratio register LCRR CLKDIV For proper operation of the local bus CLKDIV must be set...

Page 49: ...ting Motorola Computer Group s World Wide Web literature site http www motorola com computer literature To obtain the most up to date product information in PDF or HTML format visit http www motorola com computer literature Table A 1 Motorola Computer Group Documents Document Title Motorola Publication Number MVME3100 Single Board Computer Programmer s Reference Guide V3100A IH MOTLoad Firmware Pa...

Page 50: ...eference Manual Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 480 768 2130 800 521 6274 MPC8540RMRev 0 10 2003 Tsi148 PCI X to VME Bus Bridge User Manual Tundra Semiconductor Corporation 603 March Road Ottawa Ontario Canada K2K 2M5 Web Site www tundra com 80A3020_MA001_02 BCM5421S 10 100 1000BASE T Gigabit Transceiver Broadcom Corporation Web Site http...

Page 51: ...efault htm EXAR ST16C554 554D ST68C554 Quad UART with 16 Byte FIFOs EXAR Corporation 48720 Kato Road Fremont CA 94538 Web Site http www exar com ST16C554 554D Rev 3 1 0 2 Wire Serial EEPROM Datasheet Atmel Corporation San Jose CA Web Site http www atmel com atmel support AT24C512 Maxim DS1621Digital Thermometer and Thermostat Maxim Integrated Products Web Site http www maxim ic com DS1621 Maxim DS...

Page 52: ...E64 Specification ANSI VITA 1 1994 VME64 Extensions ANSI VITA 1 1 1997 2eSST Source Synchronous Transfer VITA 1 5 2003 PCI Special Interest Group PCI SIG http www pcisig com Peripheral Component Interconnect PCI Local Bus Specification Revision 2 0 2 1 2 2 PCI Local Bus Specification PCI X Addendum to the PCI Local Bus Specification Rev 1 0b IEEE http standards ieee org catalog IEEE Common Mezzani...

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