Functional Description
MVME197IG/D1A1
1-9
1
Data Bus Structure
The data bus structure is arranged to accommodate the various 8-bit, 16-bit,
32-bit, and 64-bit devices that reside on the module. Refer to the
MVME197LE,
MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference
Guide
and to the user’s guide for each device to determine its port size, data
bus connection, and any restrictions that apply when accessing the device.
MC88110 MPU
The MVME197 series of single board computers are based on the MC88000
families of RISC (Reduced Instruction Set Computer) microprocessors.
Depending on the specific MVME197 module, the MVME197 series uses the
MC88110 RISC microprocessor. Refer to the
Module Designation
section in the
beginning of this chapter for MVME197 module/processor variations and to
the
MC88110 Second Generation RISC Microprocessor User’s Manual
for more
detailed information on this device.
MC88410 Cache Controller
Depending on the specific MVME197DP/SP module version, each MC88110
microprocessor is connected directly to an MC88410 Secondary Cache
Controller. Each MC88410 controls a 256KB level two cache. Refer to the
MC88410 Secondary Cache Controller User’s Manual
and the
MCM62110 Data
Sheet
for more information on this device.
BOOT ROM
The board accommodates a 32-pin PLCC/CLCC ROM/EPROM referred to as
BOOT ROM or DROM (Download ROM). It is organized as a 256K x 8 device,
but as viewed from the processor it looks like a 32K x 64 memory. This
memory is mapped starting at location $FFF80000, but after a local reset it is
also mapped at location 0, providing a reset vector and bootstrap code for the
processor. The DR0 bit in the General Control Register (GCR) of the PCCchip2
must be cleared to disable the BOOT ROM memory map at 0. In addition, the
ROM0 bit in the ROMCR register of the BusSwitch must be cleared.
Flash Memory
4MB of flash memory is available on the board. Flash memory works like
EPROM, but can be erased and reprogrammed by software. It is organized as
32 bits wide, but to the processor it looks as 64 bits wide. It is mapped at
location $FF800000. Reads can be of any size, including burst transfers, but
writes are always 32 bits wide, regardless of the size specified for the transfer.
