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Functional Description

MVME197IG/D1A1

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Data Bus Structure

The data bus structure is arranged to accommodate the various 8-bit, 16-bit,
32-bit, and 64-bit devices that reside on the module. Refer to the

MVME197LE,

MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference
Guide

 and to the user’s guide for each device to determine its port size, data

bus connection, and any restrictions that apply when accessing the device.

MC88110 MPU

The MVME197 series of single board computers are based on the MC88000
families of RISC (Reduced Instruction Set Computer) microprocessors.
Depending on the specific MVME197 module, the MVME197 series uses the
MC88110 RISC microprocessor. Refer to the

Module Designation

 section in the

beginning of this chapter for MVME197 module/processor variations and to
the

MC88110 Second Generation RISC Microprocessor User’s Manual

 for more

detailed information on this device.

MC88410 Cache Controller

Depending on the specific MVME197DP/SP module version, each MC88110
microprocessor is connected directly to an MC88410 Secondary Cache
Controller. Each MC88410 controls a 256KB level two cache. Refer to the

MC88410 Secondary Cache Controller User’s Manual

 and the

MCM62110 Data

Sheet

 for more information on this device.

BOOT ROM

The board accommodates a 32-pin PLCC/CLCC ROM/EPROM referred to as
BOOT ROM or DROM (Download ROM). It is organized as a 256K x 8 device,
but as viewed from the processor it looks like a 32K x 64 memory. This
memory is mapped starting at location $FFF80000, but after a local reset it is
also mapped at location 0, providing a reset vector and bootstrap code for the
processor. The DR0 bit in the General Control Register (GCR) of the PCCchip2
must be cleared to disable the BOOT ROM memory map at 0. In addition, the
ROM0 bit in the ROMCR register of the BusSwitch must be cleared.

Flash Memory

4MB of flash memory is available on the board. Flash memory works like
EPROM, but can be erased and reprogrammed by software. It is organized as
32 bits wide, but to the processor it looks as 64 bits wide. It is mapped at
location $FF800000. Reads can be of any size, including burst transfers, but
writes are always 32 bits wide, regardless of the size specified for the transfer.

Summary of Contents for MVME197DP

Page 1: ...update some features Please replace the pages according to the following table and place this page behind the title page of the installation guide as a record of this change A vertical bar in the margin of a replacement page indicates a text change or addition The supplement number is shown at the bottom of each replacement page Replace Old With New v vi v vi 1 1 through 1 4 1 1 through 1 4 1 7 th...

Page 2: ...ium or stored in a retrieval system or transmitted in any form or by any means radio electronic mechanical photocopying recording or facsimile or otherwise without the prior written permission of Motorola Inc Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing ...

Page 3: ...DP and MVME197SP Single Board Computer User s Manual MVME197DP and MVME197SP Single Board Computer Support Information MVME197LE MVME197DP and MVME197SP Single Board Computers Programmer s Reference Guide MVME197BUG 197Bug Debugging Package User s Manual MVME197BUG 197Bug Diagnostic Firmware User s Manual MVME712M Transition Module and P2 Adapter Board User s Manual MVME712 12 MVME712 13 MVME712A ...

Page 4: ...Board Computers NCR 53C710 SCSI Controller Data Manual and Programmer s Guide Intel i82596 Ethernet Controller User s Manual Cirrus Logic CD2401 Serial Controller User s Manual SGS Thompson MK48T08 NVRAM TOD Clock Data Sheet The following non Motorola publications may also be of interest and may be obtained from the sources indicated The VMEbus Specification is contained in ANSI IEEE Standard 1014...

Page 5: ...ware functional description This chapter closes with some general memory maps All programmable registers used in the MVME197 module series reside in ASIC Application Specific Integrated Circuit devices that are covered in the MVME197LE MVME197DP and MVME197SP Single Board Computers Programmer s Reference Guide Model Designations The MVME197DP SP module series of the Single Board Computers are avai...

Page 6: ...ransition module The MVME197 supports the MVME712M MVME712A MVME712AM and MVME712B transition boards referred to here as the MVME712X unless separately specified The MVME197 also supports the MVME712 12 and MVME712 13 referred to as the MVME712 XX unless separately specified These transition boards provide configuration headers serial port drivers and industry standard connectors for the I O devic...

Page 7: ...local peripheral bus non DMA programmed access interface a VMEbus interrupter a VMEbus system controller a VMEbus interrupt handler and a VMEbus requester The local peripheral bus to VMEbus transfers can be D8 D16 or D32 VMEchip2 DMA transfers to the VMEbus however can be 64 bits wide as Block Transfer BLT Requirements All MVME197 boards are designed to conform to the requirements of the following...

Page 8: ...e with Direct Memory Access DMA Four serial ports with EIA 232 D buffers Centronics printer port Ethernet transceiver interface VMEbus interface VMEbus system controller functions VMEbus interface to local peripheral bus A24 A32 D8 D16 D32 BLT D8 D16 D32 D64 BLT Block Transfer Local peripheral bus to VMEbus interface A24 A32 D8 D16 D32 BLT D16 D32 D64 VMEbus interrupter VMEbus interrupt handler Gl...

Page 9: ...110 ECDM X4 DCAM Data 64 Address Bus Data Bus Data Bus 256 Memory Array 128 256 MB LAN 82596CA VMEbus VMEchip2 SCSI II NCR53710 Flash Memory PCCchip2 Address Bus Data Bus Data 32 I2 C EEPROM I2 C Bus MC88410 256KB Cache 32 MC88110 MC88410 256KB Cache 4 Serial Ports CL CD2401 BOOT ROM NVRAM RTC Figure 1 2 MVME197DP Block Diagram ...

Page 10: ...197DP and MVME197SP Single Board Computers Programmer s Reference Guide for more information The ABORT switch S2 can generate an interrupt to CPU0 via the NMI signal It is normally used to abort program execution and return to the debugger This capability is controlled via the ABORT register in the BusSwitch Refer to the BusSwitch chapter of the MVME197LE MVME197DP and MVME197SP Single Board Compu...

Page 11: ...processor is connected directly to an MC88410 Secondary Cache Controller Each MC88410 controls a 256KB level two cache Refer to the MC88410 Secondary Cache Controller User s Manual and the MCM62110 Data Sheet for more information on this device BOOT ROM The board accommodates a 32 pin PLCC CLCC ROM EPROM referred to as BOOT ROM or DROM Download ROM It is organized as a 256K x 8 device but as viewe...

Page 12: ...eference Guide for detailed programming information Battery Backup RAM and Clock The MK48T08 RAM and clock chip is used on the MVME197 This chip provides a time of day clock oscillator crystal power fail detection memory write protection 8KB of RAM and a battery in one 28 pin package The clock provides seconds minutes hours day date month and year in BCD 24 hour format Corrections for 28 29 leap y...

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