I/O Implementation
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5-3
5
All boards are available with 128KB of SRAM (with battery backup);
time-of-day clock (with battery backup); an Ethernet transceiver interface;
four serial ports with EIA-232-D DTE interface; bidirectional parallel
port; four tick timers with watchdog timer(s); four EPROM sockets; SCSI
bus interface with DMA; and a VMEbus interface (local bus to
VMEbus/VMEbus to local bus, with A16/A24/A32, D8/D16/D32 bus
widths and a VMEbus system controller).
I/O Implementation
Input/Output (I/O) signals on the MVME167P are routed to the VMEbus
P2 connector. The main board is connected through a P2/LCP2 adapter
board and cables to the transition board. The MVME167P supports the
MVME712B and MVME712M transition boards. It also accommodates
older MVME712 series transition modules, which provide configuration
headers, serial port drivers, and industry-standard connectors for various
I/O devices.
ASICs
The following ASICs are used on the MVME167P:
❏
VMEchip2 ASIC (VMEbus interface). Provides two tick timers,
a watchdog timer, programmable map decoders for the master and
slave interfaces, and a VMEbus to/from local bus DMA controller
as well as a VMEbus to/from local bus non-DMA programmed
access interface, a VMEbus interrupter, a VMEbus system
controller, a VMEbus interrupt handler, and a VMEbus requester.
Processor-to-VMEbus transfers are D8, D16, or D32. VMEchip2
DMA transfers to the VMEbus, however, are D16, D32, D16/BLT,
D32/BLT, or D64/MBLT.
❏
Petra ASIC. Supplants the MCECC chip used on previous
versions of the MVME167; provides an ECC DRAM emulation.
❏
PCCchip2 ASIC. Provides an eight-bit bidirectional parallel port.
