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Summary of Contents for MVME120

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ...A MVME120 D2 MVME120 MVME121 MVME122 MVME123 VMEbus Microprocessor Module User s Manual ICR QUALITY PEOPLE PERFORMANCE Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...RNING THIS EQUIPMENT GENERATES USES AND CAN RADIATE RADIO FREQUENCY ENERGY AND IF NOT INSTALLED AND USED IN ACCORDANCE WITH THE INSTRUCTIONS MANUAL MAY CAUSE INTERFERENCE TO RADIO COMMUNICATIONS IT HAS BEEN TESTED AND FOUND TO COMPLY WITH THE LIMITS FOR A CLASS A COMPUTING DEVICE PURSUANT TO SUBPART J OF PART 15 OF FCC RULES WHICH ARE DESIGNED TO PROVIDE REASONABLE PROTECTION AGAINST SUCH INTERFER...

Page 4: ...y Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certai n conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching ...

Page 5: ...s which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on a high to low transition MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 6: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 7: ... J7 10 ROM EPROM Device Configuration Select Header J8 10 Cache Configuration Select Headers J9 J17 14 MSR Bit 1 Source Select Header J20 15 MSR Bit 0 Source Select Header J21 16 ROM Access Time Select Header J22 17 Reset Vector Fetch Mode Select Header J24 17 Local Time out Select Header J25 19 RAM Dual Port Address Select PAL U28 19 Factory Configured RAM Dual Port Base Address 19 Changi ng U28 ...

Page 8: ...lti Port Controller 38 Bus Requester 39 Interrupt Handl er 39 VMEbus Interrupts 39 ABORT Switch Interrupts 39 MC68901 Interrupts 40 Interrupt Source and Vectors 40 Enabling Interrupts 41 VMEbus Interface 41 I O and Control 42 Module Status 43 Module Control Register 44 Timers 45 ROM 46 Source of Bus Error Exceptions 46 VMEbus BERR 46 Onboard Parity Error 47 Dual Port Lock on TAS Error 47 MMU Faul ...

Page 9: ...Diagram 49 MPU Module Parts Location 63 MPU Module Schematic Diagram 65 LIST OF TABLES MPU Module Specifications 3 Interpretation of Front Panel Indicators 24 Modul e Status 43 Connector PI Interconnect Signals 51 Connector Jl Interconnect Signals 56 MPU Module Parts List 57 iii MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 10: ... MOTOROLA THIS PAGE INTENTIONALLY LEFT BLANK iv MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 11: ... module is shown in Figure 1 1 1 2 FEATURES The features of the MPU module include MC68010 MPU MC68451 MMU optional 4Kb logical instruction cache optional Two 28 pin ROM EPROM sockets Onboard dual port RAM with byte parity Interrupt handler Status and control registers Programmable timer RS 232C serial debug port Bus requester A24 016 VMEbus interface Local RESET switch Local software ABORT switch...

Page 12: ... MOTOROLA I 2 GENERAL INFORMATION r n l U I MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 13: ...0 MHz 128Kb 512Kb Two sockets for user supplied 4K x 8 8K x 8 16K x 8 32K x 8 or 64K x 8 devices All onboard plus seven VMEbus interrupts RS 232C serial debug port terminal only o degrees C to 50 degrees C forced air is required 40 degrees to 85 degrees C 0 to 90 noncondensing 7 40 in 188 mm x 10 20 in 261 mm o 83 in 21 mm 5 Vdc typical 120 4 2 A 121 4 0 A 122 3 2 A 123 4 3 A 12 Vdc 12 rnA 12 Vdc ...

Page 14: ...ctures 1 5 MVME120 FAMILY CONFIGURATIONS Four configurations are available for the MVME120 Family of Microprocessor Modules The configurations are listed below MVME120 MVME121 MVMEl22 MVMEl23 10 MHz MC68010 128K dynamic RAM cache MMU 10 MHz MC68010 512K dynamic RAM cache MMU 12 5 MHz MC68010 128K dynamic RAM no cache no MMU 12 5 MHz MC68010 512K dynamic RAM cache no MMU The MC68451 MMU does not fu...

Page 15: ...e back of the MC68010 case below 80 degrees centigrade To select the desired configuration and ensure proper operation of the MPU module certain modifications may be made before installation These modifications are made through jumper or wire wrap arrangements on the headers Figure 2 1 illustrates the location of the headers and connectors on the MPU module The MPU module has been factory tested a...

Page 16: ... 10 00 J2 6 2 3 1 J7 160015 0 0 0 0 0 0 0 0 0 0 0 0 20 01 z 00 2 0 01 3 1 J910 0 0 J20 J21 00 8 7 00 2 001 3 LQJ1 J17 J22 FIGURE 2 1 MPU Module Option locations 0 a J1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 17: ...PARATION Bit 7 of the Module Status Register MSR can be configured to monitor either the Alternating Current Failure ACFAIL signal on the VMEbus or to monitor the System Failure SYSFAIL signal on the VMEbus ACFAIL is monitored when the jumper is positioned between pins 1 and 2 on header J2 SYSFAIL is monitored when the jumper is positioned between pins 2 and 3 J2 J2 I 0 0 0 I I 0 0 0 I 321 3 2 1 A...

Page 18: ...5 6 I 0 o I 5 I I I I I I I I I I I I I 4 0 o I 3 4 I 0 o I 3 4 I 0 o I 3 4 I 0 o I 3 I I I I I I I I I 2 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 J3 J3 J3 J3 12 I 0 o III 12 I 0 o III 12 I 0 o III 12 I 0 o III I I I I I I I I I I 10 I 0 o I 9 10 I 0 o I 9 10 I 0 o I 9 10 I 0 o I 9 I I I I I I I I 8 I 0 o I 7 8 I 0 o I 7 8 I 0 o I 7 8 I 0 o I 7 I I I I I I I I I I 6 I 0 o I 5 6 I 0 o I 5 6 I 0 ...

Page 19: ...1 I 0 I ABORT SWITCH ENABLED 2 3 4 RESET Switch Disable Select Header J6 J5 2 101 I I 1 101 ABORT SWITCH DISABLED The front panel RESET switch on the MPU module can be disabled The switch is disabled when the jumper is removed from header J6 As shown below the MPU module is shipped with the switch enabled J6 2 101 I I I 1 101 RESET SWITCH ENABLED 9 J6 2 101 I I 1 I 0 I RESET SWITCH DISABLED MICROS...

Page 20: ... IRQ2 I I 2 0 0 I 1 IRQl 2 I 0 0 1 IRQl CONNECTED DISCONNECTED 2 3 6 ROM EPROM Device Configuration Select Header J8 There are several types of ROM EPROM devices that can be used in sockets XU44 and XU52 Header J8 must be configured to match the devices used The figures below show configurations of J8 for the most commonly used devices When inserting devices into XU44 and XU52 the device containin...

Page 21: ...0 o I 7 I I 6 I 0 o I 5 I I I 4 I 0 o I 3 I I 2 I 0 o I 1 Header configuration for 8K x 8 EPROM memory devices MCM68764 MCM68766 is shown below 16 14 12 10 8 6 4 2 J8 I 0 o 115 I I I 0 o 113 I I I I 0 o III I I I I 0 o I 9 I I I 0 o I 7 I I I 0 o I 5 I I I I 0 o I 3 I I I 0 o I 1 11 MICROSYSTEMS I Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 22: ... 8 I 0 o I 7 I I I 6 I 0 o I 5 I I 4 I 0 o I 3 I I 2 I 0 0 I 1 Header configuration for 16K x 8 EPROM memory devices AM27128 INT27128 is shown below J8 16 I 0 o 115 I I 14 I 0 0 113 I I 12 I 0 0 III I I 10 I 0 0 I 9 I I 8 I 0 o I 7 I I I 6 I 0 o I 5 I I 4 I 0 o I 3 I I 2 I 0 0 I 1 12 MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 23: ... 0 0 5 4 0 0 3 2 0 0 1 Header configuration for 64K x 8 EPROM memory devices AM27512 is shown below J8 16 0 0 115 I 14 0 0 113 I 12 0 0 111 I 10 0 0 I 9 I 8 0 0 I 7 I 6 o X o THE CIRCUIT TRACK ON THE I BACK OF THE MODULE MUST 4 0 0 I 3 BE CUT I 2 0 0 I 1 13 MICROSYSTEMS I Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 24: ...er position on headers J9 and J17 determine what mode is selected as shown below J9 J17 I 0 0 0 I 3 I 0 I I I 3 2 1 2 I 0 I I I I 1 I 0 I ALL 4KB OF CACHE ARE USER ONLY J9 J17 I 0 0 0 I 3 I 0 I I I I 321 2 I 0 I I I 1 I 0 I ALL 4KB OF CACHE ARE SUPERVISOR ONLY J9 I 0 0 0 I 321 J17 3 101 I I 2 101 I I 1 I 0 I ALL 4KB OF CACHE ARE MIXED USER AND SUPERVISOR 14 MICROSYSTEMS Artisan Technology Group Qu...

Page 25: ...d then cache is disabled When section 1 is open the signal line CACHERR can be monitored but this is not a useful configuration Header configurations and switch settings are shown below S3 111X 101 I FI 121 IFI I II 131 101 I PI 141 IEI I NI MSR BIT 1 0 J20 2 I 0 I I I 1 101 S3 111 XIOI I FI 121 IFI I II 131 101 I PI 141 lEI I NI MSR BIT 1 1 15 S3 111X 101 I FI 121 IFI I II 131 101 I PI 141 lEI I ...

Page 26: ...to the signal CACHEHIT it matches the level of CACHEHIT Header and switch configurations are shown below J21 3 101 I I I 2 I 0 I I I 1 I 0 I SECTION 2 OF S3 CONNECTED TO BIT 0 OF THE MSR S3 53 III 101 III 101 I FI I FI 121X IFI 121 XIFI I II I II 131 101 131 101 I PI I PI 141 IEI I I lEI I NI I NI MSR BIT 0 0 MSR BIT 0 1 16 J21 3 101 I I 2 101 I I I 1 101 CACHEHIT CONNECTED TO BIT 0 OF THE MSR MIC...

Page 27: ...I I I I 4 I 0 o I 3 4 I 0 0 I 3 4 I 0 o I 3 4 I 0 o I 3 I I I I I I I I 2 I 0 0 I 1 2 I 0 o I 1 2 I 0 o I 1 2 I 0 o I 1 ROM ACCESS TIME ROM ACCESS TIME ROM ACCESS TIME ROM ACCESS TIME LESS THAN OR LESS THAN OR LESS THAN OR LESS THAN OR EQUAL TO EQUAL TO EQUAL TO EQUAL TO MVME 120 121 123 N A 250 ns 350 ns 450 ns MVME 122 200 ns 400 ns 450 ns 500 ns 2 3 11 Reset Vector Fetch Mode Select Header J24 ...

Page 28: ...FI 121 IFI I II 131 XIOI I PI 141 X IEI I NI FETCH RESET VECTORS FROM VMEbus ADDRESS MODIFIER lE S3 III 101 I FI 121 IFI I II 131X 101 I PI 141 X IEI I NI FETCH RESET VECTORS FROM VMEbus ADDRESS MODIFIER 16 18 S3 III 101 I FI 121 IFI I II 131 XI 0I I PI 141 XI EI I NI FETCH RESET VECTORS FROM ONBOARD S3 III 101 I FI 1211 FI I II 131X 101 I PI 141 XIEI I NI FETCH RESET VECTORS FROM ONBOARD MICROSYS...

Page 29: ... MUST BE LESS THAN OR EQUAL TO 200 MICROSECONDS The onboard RAM of the MPU Module is accessible by the onboard MPU and by ot er VMEbus masters The lower address at which the onboard RAM appears for the VMEbus master is called the RAM dual port base address The RAM dual port base address is controlled by the program in the PAL in socket U28 The PAL can be programmed to place the RAM dual port base ...

Page 30: ...UAL PORT MAP DECODER 128KBYTE ONBOARD RAM SET FOR VMEBUS ADDRESSES 0 lFFFF PAL16L2 U28 SHEET 8 PALDP21 MVME121 MVME123 A23 A22 A21 A20 A19 Al8 A17 LWORD IACK GND AMI AM3 AM2 AM4 15 DPMATCH AMO AM5 VMEAV VCC DPMATCH A23 A22 A21 A20 A19 OOOOOO 07FFFF IACK LWORD VMEAV AM5 AM4 AM3 AM2 AM1 AMO STANDARD PRIV PROG A23 A22 A21 A20 AI9 OOOOOO 07FFFF IACK LWORD VMEAV AM5 AM4 AM3 AM2 AM1 AMO STANDARD PRIV DA...

Page 31: ... ADDRESS 80000 FFFFF ADDRESS lOOOOO 17FFFF ADDRESS 180000 lFFFFF SAMPLE ADDRESS LINES FOR 1 2MBYTE OF ONBOARD RAM 2 4 INSTALLATION The following paragraphs discuss installation of the MPU module into a VME chassis and the connection of an RS 232C cable Before inserting the module into the VMEbus chassis ensure that the desired EPROM ROM devices are installed and configured and that all other heade...

Page 32: ...s indirectly except for the IACKIN IACKOUT signal lines which it connects directly so that none of the daisy chain signal lines should be shorted on the backplane at the slot where it resides d Carefully slide module into card slot Be sure module is seated properly into connectors on the PI backplane Fasten module in chassis with front panel screws provided e Make sure that all devices on the VMEb...

Page 33: ...ly reset by SYSRESET 3 2 2 ABORT Switch A software ABORT switch is located on the front panel Programs may be aborted with this switch Oepressing this switch causes a level 7 interrupt to be input to the MPU The ABORT switch does not abort the MPU during the execution of the STOP instruction 3 2 3 Mode Switch The mode switch section 4 of S3 provides the ability through hardware for the MPU to fetc...

Page 34: ...s Strobe AS pin of the MPU is true and off when it is false Refer to Table 3 1 for details TABLE 3 1 Interpretation of Front Panel Indicators FAIL HALT RUN DESCRIPTION OFF OFF ON ON ON ON OFF OFF ON OFF OFF ON OFF ON OFF ON OFF ON No power applied to the module or processor running but is not the local bus master Normal operation Module is being reset or MPU has halted usually the result of a doub...

Page 35: ...10000 I RESERVED FOR ONBOARD ROM EXPANSION F1FFFF I F20000 I RESERVED 1 I MFP GPIP F20002 I RESERVED 1 I MFP AER F20004 I RESERVED 1 I MFP DDR F20006 I RESERVED 1 I MFP IERA F20008 I RESERVED 1 I MFP IERB F2000A I RESERVED 1 I MFP IPRA F2000C I RESERVED 1 I MFP IPRB F2000E I RESERVED 1 I MFP ISRA F20010 I RESERVED 1 I MFP ISRB F20012 I RESERVED 1 I MFP IMRA F20014 I RESERVED 1 I MFP IMRB F20016 I ...

Page 36: ...E F40000 1 VME120 1 RESERVED I CONTROL REGISTER 1 F40002 1 VME120 1 1 CONTROL REGISTER 1 RESERVED F5FFFF IREPEATS IN THIS SPACE 1 F60000 1 MMU AST 0 2 1 RESERVED F60002 1 MMU AST 1 2 I RESERVED 1 F60004 I MMU AST 2 2 1 RESERVED 1 1 F60006 1 MMU AST 3 2 1 RESERVED F60008 1 MMU AST 4 2 1 RESERVED F6000A 1 MMU AST 5 2 1 RESERVED F6000C 1 MMU AST 6 2 1 RESERVED F6000E 1 MMU AST 7 2 1 RESERVED F60010 1...

Page 37: ...VR 2 F6002C 1 RESERVED 1 MMU GSR 2 1 F6002E 1 RESERVED 1 MMU LSR 2 F60030 1 RESERVED 1 MMU SSR 2 1 F60032 1 RESERVED 1 RESERVED F60034 1 RESERVED 1 RESERVED F60036 1 RESERVED 1 RESERVED F60038 1 RESERVED 1 MMU lOP 2 F6003A 1 RESERVED 1 MMU RDP 2 1 F6003C 1 RESERVED 1 MMU DIRECT 1 1 1 TRANSLATION 1 1 F6003E 1 RESERVED LOAD DESCRIPTOR 1 1 F60040 1 THE ABOVE MMU REGISTERS OCCUR 1 F7FFFF 1 REPEATEDLY ...

Page 38: ...if the MMU is present accesses to these locations when no MMU is present causes the MPU module to hang up until reset occurs 3 3 1 MPU Module Memory Map as Viewed from the VMEbus The onboard RAM appears to the VMEbus at the base address programmed into U28 The factory configuration of U28 causes the base address of onboard RAM as viewed from the VMEbus to be 000000 If U28 is changed refer to parag...

Page 39: ...to complete the column addressing The lowest nine address lines are always required to be nontranslatable with this mode of operation and restricts memory segmentation to a minimum size of 1024 bytes Programs are aborted by depressing the ABORT switch on the front panel of the module Depressing this switch interrupts the MPU at level 7 The module is reset whenever the entire system is reset SYSTEM...

Page 40: ... a pin grid array package is the modules engine The MPU and its associated circuitry are designed to run at 12 5 MHz The clock is a 25 MHz oscillator divided by a flip flop Although the circuitry is designed to run at 10 MHz or 12 5 MHz depending on the version of the module 4 3 2 MMU The MMU is an MC68451 in a pin grid array package The MMU is able to translate A8 A23 of the processor However to ...

Page 41: ...1K word of user space cache and 1K word of supervisory space cache Configurations a b c each have one bank of 2K entries Configuration d has two banks of lK entries each Each entry within cache is addressed by the MPU lower address lines AI AID for configuration d or AI All for configurations a b c These lower address lines are called the index For every possible index value there is a unique cach...

Page 42: ...nally copied from main memory FC2 1 for supervisory address space and 0 for user address space This organization of cache is called single set associative It causes each entry in cache to align itself with specific main memory locations For example for configurations a b c cache entry 1 index 000 is only capable of caching memory locations 0 1000 2000 3000 etc Cache entry 4 index 006 is only capab...

Page 43: ...ory access cycle except for cache flush operations The cache does not perform any function during RAM refresh cycles or VMEbus to RAM access cycles At the beginning of each processor memory access cycle before any devices on the module can be selected the MPU lower address lines index a specific entry in the cache The valid bits for that entry are checked and the tag from that entry is compared to...

Page 44: ...is being driven onto 000 015 by the selected device into the cache data word d The cache latches the value that is being driven onto All or AI2 and FC2 by the MPU into the cache tag e The cache sets VI and V2 in the cache tag f The MPU finishes the cycle with the number of wait cycles indicated by the selected device Cache Invalidate Cycle When the cache has determined that the current cycle is a ...

Page 45: ...pervisory data space always causes a cache ignore cycle c Write to user data space causes a cache invalidate cycle if the cache entry addressed by the index has all of the following 1 Both VI and V2 are true 2 The cache tag address matches the current upper logical address from the MPU 3 The F bit in the tag is o Otherwise write to user data space causes a cache ignore cycle d Write to supervisory...

Page 46: ...he when changing descriptors in the MMU Problem 4 The software uses PC relative reads of data that appears as program space on the function code pins of the MPU It writes to that data in another address space and then it uses PC relative reads of those same logical addresses expecting to have updated information Solution Avoid the use of PC relative instructions for data that is to be altered or f...

Page 47: ... MPU for mastership of the onboard local bus When the MPU gives up local bus mastership the MPC gives bus mastership to either the RAM refresh control logic or the VMEbus In the event of simultaneous requests refresh has the highest priority The MPC also handles MPU VMEbus lock conditions The lock occurs when the onboard MPU attempts to access the VMEbus at the same time a VMEbus master attempts a...

Page 48: ...nboard MPU the ability to sense and respond to all onboard interrupts all seven VMEbus interrupts VMEbus ACFAIL SYSFAIL and the ABORT switch All the onboard interrupts and ACFAIL SYSFAIL interrupt the MPU indirectly via the MC68901 The VMEbus interrupts and the ABORT switch interrupt the MPU directly All interrupt requests to the MPU are disabled by the IE bit in the MCR 4 3 7 1 VMEbus Interrupts ...

Page 49: ...VE I I VMEbus IRQ2 I DIRECT I SAME AS ABOVE I 4 XVECTOR I 2 VMEbus IRQ3 I DIRECT I SAME AS ABOVE I 4 XVECTOR I 3 VMEbus IRQ4 I DIRECT I SAME AS ABOVE I 4 X VECTOR I 4 VMEbus IRQ5 I DIRECT I SAME AS ABOVE I 4 XVECTOR I 5 VMEbus IRQ6 I DIRECT I SAME AS ABOVE I 4 XVECTOR I 6 SECTION 2 J21 2 3 IMC68901 I REFER TO MC68901 I 4 XVECTOR I 6 NOT DEBOUNCED I GPIOO I DATA SHEET I I CACHEHIT J21 1 2 I I I I S...

Page 50: ...ET I I ACFAIL J2 1 2 IMC68901 I REFER TO MC68901 I 4 X VECTOR I 6 SYSFAIL J2 2 3 I GPI07 I DATA SHEET I I VMEbus IRQ7 I DIRECT I FROM INTERRUPTING I 4 X VECTOR I 7 I I VMEbus SLAVE I I ABORT I DIRECT I NONE I 7C I 7 4 3 7 5 Enabling Interrupts VMEbus interrupts are enabled disabled using jumpers ABORT is enabled disabled using a jumper and all interrupts that come through the MC68901 are enabled i...

Page 51: ...gram access 3D Standard supervisory data access 3A Standard non privileged program access 39 Standard non privileged data access 4 3 9 I O and Control The serial port timers and module status are implemented using an MC68901 multifunction peripheral device and some additional control logic Details of the MC68901 can be found in the MC68901 data sheet The device is capable of generating 16 internal...

Page 52: ...1 of S3 is open and low when it is closed VMEBERR pulses high momentarily when the VMEbus BERR signal line goes true It is low at all other times PARERR pulses high momentarily during an onboard RAM read cycle that results tn a parity error It is low at all other times Mode is low when the MPU module is configured to fetch its reset vectors from the VMEbus and high when it is configured to fetch t...

Page 53: ... BIT 4 I BIT 3 I BIT 2 I BIT 1 I BIT I I Wwp I ALTCLR I FREEZE I CACHEN I PAREN I IE I CTS IBRDFAIL I BIT 7 WWP when 0 causes faulty parity to be stored when any good onboard RAM location is written to by the MPU When the same location is read a parity error occurs WWP when 1 allows correct parity to be written by the MPU Correct parity is defined as being odd BIT 6 ALTCLR when 1 allows bus error ...

Page 54: ... address Immediately after reset all control register bits are set to logic 1 by hardware 4 3 9 3 Timers Four timers are provided onboard through the MC68901 and each timer is capable of generating an interrupt For detailed information refer to the MC68901 Data Sheet The timers are assigned as follows Timer C Baud rate generator for the serial port Timer A Software tick timer Timer B Tick timer ov...

Page 55: ...module is reset if the mode switch is in the normal position disabled prior to the reset the MPU fetches its reset stack pointer and program counter from the first eight bytes of onboard ROM Writes to ROM do not cause a bus error exception to occur 4 3 11 Source of Bus Error Exceptions There are several sources of bus errors Some of the sources are fatal errors while others are not The MSR can be ...

Page 56: ...cessor rerun 4 3 11 4 MMU Fault MMU fault is not a status bit in the MSR but is available as status in the MMU This bus error exception occurs whenever the MMU drives its FAULT pin low 4 3 11 5 Local Bus Time out Local bus time out is not a status bit This bus error exception occurs when VMEbus mastership is not attained in the alloted time Local bus time out should be rerun with a processor rerun...

Page 57: ... yMOTOROLA FUNCTIONAL DESCRIPTION II THIS PAGE INTENTIONALLY LEFT BLANK 48 MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 58: ...BUS INTERFACE DUAL PORT MAP DECODER L r r ADDRESS BUS DATA BUS PI r o c _ _ _ _ S E LE C T B U S _r_r _ L ____ r 1 C O N T RO L B U S I SERIAL PORT INTERRUPT HANDLER 1 _ _ 1 STATUS REGISTER 1 ___ TIMERS 7 6 CONTROL REGISTER ABORT SWITCH 5 t ROM PROM IEPROM SOFTWARE READABLE SWITCHES 4 FIGURE 4 1 VME BUS REOUESTOR IRO AND STATUS BUS BLOCK DIAGRAM 63DW Q38 REV 8 SH 2 MPU Module Block Diagram OF 15 4...

Page 59: ...eristic for the connector TABLE 5 1 Connector PI Interconnect Signals PIN NUMBER SIGNAL MNEMONIC SIGNAL NAME AND DESCRIPTION AI A8 A9 AID All A12 A13 A14 A15 000 007 GND GND DS1 DSO WRITE GND DATA bus bits 0 7 eight of 16 three state bidirectional data lines that provide the data path between VMEbus master and slave GROUND Not used GROUND DATA STROBE 1 signal driven by VMEbus master that indicates...

Page 60: ... acknowledging the specific interrupt with a service routine INTERRUPT ACKNOWLEDGE IN IACKIN and IACKOUT form a daisy chained acknowledge The IACKIN signal is connected directly to IACKOUT INTERRUPT ACKNOWLEDGE OUT IACKIN and IACKOUT form a daisy chained acknowledge The IACKOUT signal is connected directly to IACKIN ADDRESS MODIFIER bit 4 one of the three state lines driven by VMEbus master that p...

Page 61: ... daisy chained bus grant A grant received at the jumpered level indicates the MPU module may become the bus master The remaining three bus grant in lines are connected directly to their respective bus grant out lines BUS GRANT bit 0 OUT bus grant in and bus grant out form a daisy chained bus grant When a bus grant in is received at the jumpered level and the MPU is not awaiting bus mastership the ...

Page 62: ... INTERRUPT REQUEST 7 1 seven prioritized interrupt request inputs Jumper enabled level seven is the highest priority Not used S Vdc Power same as S VDC on pin A32 DATA bus bits 8 1S eight of 16 three state bidirectional data lines that provide the data path between VMEbus master and slave GROUND SYSTEM FAIL signal driven by the MPU module when fail bit is true in MCR Also can be monitored in MSR B...

Page 63: ...same as A07 on pin A24 ADDRESS bus bit 21 same as A07 on pin A24 ADDRESS bus bit 20 same as A07 on pin A24 ADDRESS bus bit 19 same as A07 on pin A24 ADDRESS bus bit 18 same as A07 on pin A24 ADDRESS bus bit 17 same as A07 on pin A24 ADDRESS bus bit 16 same as A07 on pin A24 ADDRESS bus bit 15 same as A07 on pin A24 ADDRESS bus bit 14 same as A07 on pin A24 ADDRESS bus bit 13 same as A07 on pin A24...

Page 64: ...he MK68901 peripheral chip Refer to Mostek data sheet for details TABLE 5 2 Connector Jl Interconnect Signals PIN NUMBER SIGNAL MNEMONIC SIGNAL NAME AND DESCRIPTION 1 2 3 4 5 6 7 8 9 19 20 21 25 TxD RxD CTS DSR SIG GND DCD DTR Not used TRANSMIT DATA data to be transmitted is furnished on this line to the MVME120 RECEIVE DATA data from the receive line is presented to the terminal Not used CLEAR TO...

Page 65: ...C4 C5 21NW9632A03 Capacitor fixed ceramic 0 1 uF 50 Vdc C7 C17 C19 C22 C24 C25 C27 C29 C49 C51 C53 C55 C66 C68 C23 DLl DL2 DL3 DS1 DS2 DS3 J1 J2 J9 J17 J21 J24 J3 J4 J5 J6 J20 J7 23NW9704A99 Capacitor tantalum 33 uF 15 Vdc 01NW9804C33 Delay module triple 40 ns 01NW9804C12 Delay module triple 20 ns 01NW9804c34 Delay module triple 70 ns 48NW9612A49 Indicator LED red 48NW9612A59 Indicator LED green 2...

Page 66: ...esistor network 7 10k ohm R25 R8 R29 5lNW9626A22 Resistor network 5 10k ohm R9 51NW9626A4l Resistor network 9 4 7k ohm RIO 51NW9626B55 Resistor network 9 4 7k ohm Rll 5INW9626B52 Resistor network 5 l0k ohm R12 51NW9626A63 Resistor network 5 2 2k ohm R13 51NW9626B56 Resistor network 9 l0k ohm R14 5lNW9626B51 Resistor network 5 lk ohm R15 5lNW9626B49 Resistor network 9 l5k ohm R16 06SW 124A17 Resist...

Page 67: ...C6882L U6 51NW9615F79 I C SN74S240N U7 NOTE I C programmed Ull U18 51NW9615F85 I C SN74S38N U12 51NW9615N76 I C SN74LS652NT U13 U14 51NW9615K98 I C 74F280PC U15 51NW9615G38 I C SN74LS38N U16 NOTE I C programmed U17 U22 51NW9615K18 I C 74F373PC U20 51NW9615E93 I C SN74LS14N U21 NOTE I C programmed U23 51NW9615C30 I C SN74LS193N U24 U29 U32 51NW9615R26 I C SN74ALS645 1N U25 U66 UI0l 51NW9615K73 I C ...

Page 68: ...901 U37 51NW9615F30 I C DM74S05N U38 SlNW961SD93 I C SN74S30N U39 NOTE I C programmed U40 NOTE I C programmed U41 U49 SlNW9615H79 I C TMM2016P 1 used on 120 121 123 U42 U83 U9S SlNW9615K70 I C 74F08PC U107 U47 SlNW961SL74 I C 74Fl63PC U48 U59 SlNW961SN32 I C 74F164PC U50 US1 U53 51NW961SN4S I C 74F257PC US4 SlNW961SK6S I C 74F64PC USS U70 SlNW961SK71 I C 74F04PC US6 NOTE I C programmed US7 SlNW961...

Page 69: ...79 U80 U85 U86 U91 U92 U97 U98 UI03 U104 UI09 UllO U63 51NW9615N47 I C MC3488API U65 51NW9615F38 I C SN74LS393N U7l 51NW9615K67 I C 74F20PC U89 51NW9615K68 I C 74F11PC U94 51NW9615D26 I C SN74S113N U105 51NW9615B30 I C MC1489AP U108 NOTE I C programmed VI 48AW1068B03 Crystal oscillator 20 0 MHz used on 120 121 VI 48AW1015Bll Crystal oscillator 25 0 MHz used on 122 123 09NW9811A78 Socket DIL 20 pin...

Page 70: ... at U35 09 W4659BI2 Socket I2 pi n use at U4I U49 09 W4659BI4 Socket I4 pin use at UX44 UX52 09NW98IIA46 Socket crystal 4 1ead use at YI 55NW950IAI2 Handle 64 W4736BOI Panel front 29NW9805BI7 Jumper shorting insul ated use at J2 J9 JI7 J20 J24 J25 NOTE When ordering use number labeled on part 62 MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg co...

Page 71: ...24 T U2S U2I U21 f U2 IfCl cr l ulO 0 0 f Uti fm I C20 C21 L C21 UII It UI4 RII I o Oll A1S iCJ CJ Ol2 r I f C a I D UIO n I f 1 on u U11 c471 f U14 c 1 U15 I f T F U1 R21 Ull r hM r UI2 U14 CSI UI1 RU r UII U O UI UIOO Ul021 fcu Ul01 cill f Ul0 I i If If lOS Ul01 UI07 NOI1VW OjNI l Oddns OI lO LOW GiJ Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 72: ...PPORT INFORMATION 5 4 SCHEMATIC DIAGRAMS FIGURE 5 2 illustrates the schematic diagram for the MPU module I 64 MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 73: ...74LS64 i 1 10 20 i2 U33 74F74 7 14 12 15 U34 PAL20L8A 12 24 7 U35 MK68901 36 II 15 _V i6 74F74 7 14 9 1 137 7 7 14 4 8 11 12 U38 74S30 7 14 11 U39 PAL20L3A 12 _2 15 U40 PALl6L8B 10 20 5 U41 MCM65116 12 46 U42 74F08 7 14 47 1112 U43 74FI1 7 14 4 9 U45 74F32 7_J 14 3 9 12 u l6 74F32 1 14 4 11 U47 74F163 8 ___ 16 4 U48 74F164 7 14 12 U49 MCM65116 12 24 6 Us0 74F2S7 Jl L6 10 U51 74F257 8 16 l U53 74F2...

Page 74: ...1 CONTROL BUS INTERF ACE o SE L E C T B U S _ 1 t ft i 1 L______ r J C O N T R O L_ BU S __ _ __ I __ ___ _ ___ r I PI SERIAL PORT INTERRUPT HANDLER I STATUS REGISTER 1 ___ CONTROL REGISTER ROM PROM EPROM VME BUS REQUESTOR 7 TIMERS ____________________ _____ ___________________________ __________I R Q AND STATUS BUS ABORT SWITCH 6 5 t SOFTWARE READABLE SWITCHES FIGURE 5 2 BLOCK DIAGRAM 63DW 2 3B R...

Page 75: ... 1 R13D 1 R13E 10K 10K 10K 3 5 6 NC NC NC INC V U105A MC1489 NC R8A 10K 2 2 NC UllJ58 U2E MC1489 5244 NC NC NC 6 5 t 4 3 o IC10 ICll Tc12 IC13 IC14 IC15 IG16 5V 1 1 1 1 1 1 916 IC32 1 IC33 1 IC34 1 IG35 IC36 IC37 1 1 1 Ic c39 1 1 IC52 IC53 TC55 lCss IC57 IC58 lC59 1 1 1 1 1 1 1 1 V C I I 1 7 9 11 r r 12 TT TTTT NC 1 R14D 1 R15J 5fR17C 1 R238 1 R25G 1 R29A 1 R29D lK 15K 47 10K 10K 10K 10K 5 10 6 3 ...

Page 76: ..._ il A10 W fll 1 i AI4 J A15 All A16 f LLL L u 1 A17 GI0 AP 8 A18 ft A p J B 1 1i i f C K A19 h r _ _ _ _ 8 2 t TIT t2 r RLW A22 CQ A2 7C7 10D7 o c NC U30A U30B U20A 4 F74 10 F74 r AS A23 K3 FC0 FC0 J3 1FCil 23 A BUS 5C7 6D7 12A7 14C7 8C3 8D3 8C3 15B3 1583 15B3 1583 6C3 383 ft R5 L 2 J6J 10 l L 142 VV Ir L ___ _ 1 tn 2 D PR 011 5 1 112 1 D PROW NC IC23 1 I CK O r NC WLI CK O B 3 CLR CLR 76V I 13 I...

Page 77: ...PE Pf QL PE PE 1 L 1 I iR E S EJ T r t t r__ RESET 3 RESE T 13 13 _ UI02 US6 USfiJ U84 4 I W_ _ 2 fATi9M Sc 2 15 Q0 H AAI J 2 2 2 S 2 A I 22 TMS215 21 22 TMS215fiJ A21 2 r O _ p A2 W 1 _ _ __ 2 5 3 r t t FA 2 11 Ai 2S 3 r H J FA 2f 1 _ _ 2 r H t A 2n A 2 12 A2 tA2 02HH I AWI t lH 4HA2 0 2 2 A2 02 2 A2 D2H t 7A 2 n 1 _ H iA3 03 1 A3 D3 A3 03 A3 03f i W A4 04 CA A4 D4 A A4 04 I A A4 04HoH l U l A v ...

Page 78: ...____ __________ 3 __ __ 1 IIH I 4BJ lAS i r _____ ISJ tlUt C 8 lOP GHTI 58J UUTCHJ IUS l83I VWEAV7t J 403 r 1I1 1 In Alit J 4B3 l 1 3 t t J 783 t 1 1 II JV I A 2 3 fDl IIUlII 4C3 l lIIftlWlt t ______ Hi 7 T 63DW3293B RfV E SH 6 OF 15 7 6 5 t FIGURE 5 2 MPU Module Schematic Diagram D c B 75 76 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 79: ...1 El RSS A041 D2 RS4 A031 Dl A02 C I RS3 1 A 0 1 C 2 1RS2 ____ U j RSI 1r _ B 8 1 FC3 I A9 FC2 87 FCI A8 EQ 0 82 CS ED AS HAD 10 WIN D9 4700 0 R90 47011 5 1 R9F 4700 5V 5V 5V ____Ir_ _ 8713 _ __ f__ B S UDS J s 1 3 LO _ __ r r 8 llyR W A3 ANY B4 ALL A2 7 1 RlW J MFPOMMU J FAULT l 4 l B Q QIACK r IRa SV 5V 1 5V 1 RESET MODE 1 RESET J R9C R9G R9E 4700 4700 4700 S 6 186 IC9 r r 1_r NC 4 U420 COT ACK ...

Page 80: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 81: ... P CKO 8 CLR 3 CLR CLR 13 WPRI60 l IIB7 10K 5 v I V 1 r 6 i 13 I l3 RASI60 8C7 I1B7 2 I 5V Jru LQl 403 MPUCL _ _ _rI l I L j _ I ____ 1 ____ __ __ ____ _______________ 687 I0C7 RI4E U93B Sv I AI KfIr R188 __________________ 1 __________ 6 _ L l__ ____ Aw41 171r _____ u Ru lA Si 10B7 1207 U89B 10 F74 t H A 4 FI1 4B3 R W l 5 6 12 PR I 0 4B3 31 J fD Qi NC U101B 1Lp CK Q 8 5 F00 6 13C3 CPU Cl U70F F04...

Page 82: ... A3 RJ i A IH 1 A4 RA 13 A5 RA 9 A6 RAE J A7 RW 3 8 RAS 4 YL U 7 AI CSi c rl5 Ws 3 RA0l RAlJ RA21 RA3 RA5l RA7 RA8J RHPAR 1187 U103 Ul 9 MCM6256 2 14 MCM6256 A IJ 5 r 01 0 0 tA 7 A tA 6 Al tA 12 A2 tA 1 A3 R A4 R J 3 A5 A6 l R 7 fA f RJI 6 1 4 A8 RW J 3 iii eRAS 4 W U AS 15 CAS 16 0 BUS 4C3 tRLPARl 1187 r U62 r U69 r U75 r UBt r UB6 12 14 MCM6256 12 f4 MCM6256 12 14 MCM6256 12 14 MCM6256 12 14 MCM...

Page 83: ... 9 I S II 2 16 18 I 17 3 RIC J 14 I K r FC2 l I 5 4 I C l __ 2 5V E 19 E _ UI3 F280 ODD R21F i 5V 10K EVEN I 7 UI4 US88 F280 6 2 U4SC 4 9 Q 2 l ad 8 ODD H J 5 2 J13 EVEN I ON PARITY EN _ 14 U64A U2S0 F74 OLL 2 0 PR a S 1 U42A 3 a c6 I CK OL2C CLR F 8 20NS r 3 5 8 2 J b U648 U4S8 F74 5 t2 0 PR a 9 4l 6 n CK a 8 CLR r3 5 t 4 FIGURE 5 2 AMS AM3 AM4 AM2 AMI AM 3 _ M Q lli IS07 iT 2IO ISC7 10K 5V I 5 U...

Page 84: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 85: ... 2 5 O Q I J CI ob e i C R I R2JE r I i I J 11K 5V e 5 I I IIC OIlT PI II11 I 11 J4fi I IIC 50UT PI 1I11 2 I tPu Cl UIIIIB I FIt 5D ee fV DR i 1R13J I I I Ilfl I I I ua2B BIISYl nl I F74 I IS7 I I c U s 3 8e B I o PR o ______ __ L1 I IOo CK o JTi f e _ L J p e5l r 1 __ JBUiBLilS X __ fEJ B uly lCbRI I 3 I 807 _1 l _ IJ P UL All eC7 11 A7 tYMEAY7 1 1287 687 tYMEAYI eC7 12B tYMEAY 1 ItC7 12B7 AS l7C...

Page 86: ...ll __ ____lI 00 06 17 05 8 02 01 05 16 041 02 04 G N 0 0 3r II 0 01 3 t t t r t t 1 XU44 SOCKET 5V 3 2 16 f f f 0 CD Pll Ci 8 _ P 2L J___ c _____ vpP VCC 7 P27J e _ A 8 A12 PG MH 7 J P 216Jf 4 l AI 7J A7 NC l AI0 9 6J A6 A81 A I 0 f J V 1 1 1 R15E RI5G 15K 15K 8 9 C 1 1 1 1 1 R15H R15F R150 oR15A RI5B R15e 15K 15K 15K 15K 15K 15K 7 e 5 2 c 8 f 18 A 5 J f A5 A91H P 2L f 3J 1 A A4 2 A J A3 A A 9 A2 ...

Page 87: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 88: ...onnect a terminal to a modem When computers are connected to computers without modems one must be configured as a terminal and the other as a modem Because computers are normally configured to work with terminals they are said to be configured as a modem Also the signal levels must be between 3 and 15 volts for a high level and between 3 and 15 volts for a low level Any attempt to connect units in...

Page 89: ...gnals at the modem interface DATA CARRIER DETECT Sent by the modem to the terminal to indicate that a valid carrier is being received Not used TRANSMIT CLOCK This line clocks output data to the modem from the terminal Not used RECEIVE CLOCK This line clocks input data from a terminal to a modem Not used DATA TERMINAL READY A signal from the terminal to the modem indicating that the terminal is rea...

Page 90: ...to RTS or to some source of 12 volts such as the resistors shown in Figure 1 It is also frequently jumpered to an MC1488 gate that has its inputs grounded the gate is provided for this purpose Another signal used in many systems is DCD The original purpose of this signal was to tell the system that the carrier tone from the distant modem was being received This signal is frequently used by the sof...

Page 91: ...1l_ _ _ _ D __ O I I I I 6850 L ______ _ TXDI l RXDI RTS r 39kll 12V V N J CTS 1 DCDI I b 12V I I l J L c 58J 12V _ 4Z70 1l _ 12V 39kll DULE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ V_ _ _ _ _ _ _ _ _ _ FIGURE 1 Middle of the Road RS 232C Configuration RS 232C CONNECTO I TO MODEM OR EXORciser OR EXORmacs DCE Another subject that needs to be considered is the use of ground pins There are two pins labeled GND ...

Page 92: ... connection for pin 1 Normally pin 7 should only be connected to the CHASSIS GROUND at one point and if several terminals are used with one computer the logical place for that point is at the computer The terminals should not have a connection between the logic ground return and the chassis RS 232C CONNECTOR GriD 1 0 TXD 2 0 RXD 3 0 RTS 40 CTS 5 DSR 6 GNO 7 OeD 8 JTR20 0 1 FIGURE 2 Minimum RS 232C...

Page 93: ... MOTOROLA APPENDIX A I THIS PAGE INTENTIONALLY LEFT BLANK 100 MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 94: ... FREEZE ITAG3wT IwRITE SwX ITAG2WT ITAG1wT ICACHHIT IDATAWT ITAGOWT VCC IF YCC CACHHIT AS PROG MATCH CACHERR CACHE IF Yec DATAWT AS SEDT40 PROG FREEZE MATCH AS2 CACHE AS 3EDT40 PRDG FREEZE CACHERR AS2 CACHE AS BEDT40 MATCH AS2 CACHE WRITE ISEOT40 DATAWT ISWX AS DATAwT IF VCC TAGOWT DATA T AS A10 8ANKSEL SWX DATA T AS A10 BANKSEL BEDT40 IF vCC TAG1wT DATAWT AS A10 BANKSEL SWX DATAWT AS A1Q BANKSEL ...

Page 95: ...WT CATAwT AS A10 BANKSEL SwX DATAwT AS A10 BANKSEL r BEDT40 IF VCC TAG3WT DATAwT AS A10 8ANKSEL S X DATAWT AS A1J 5ANKSEL BEDT40 DESCRIPTION CACHE CDNTROLLER PAL PAL16L8A U1 DB SHEET 6 PALMAr 11 0 84 CK M 3823 R V B MATCH4L MATCH2U MATCHZL IBR MATCH3U MATCH3L COLUMN A1C SANKSEL GND DPGNT BRAV ISETUP VMEAV70 MATCH1U MATCH1L MATCH4U OPCASDIS TGGMATCH VCC IF VeC TAGMATCH IA10 IBANKSEL MATCH1U MATCH1L...

Page 96: ...NOT PPESENT PAL16L8A u108 SHEET 6 PALMATZ3 MVME1Z3 11 6 i4 CKSM 3823 ReV A MATCH4L MATCH2U MATCrl2L tBR MATCH3U MATCH3L COLUMN A10 BANKSEL GND DpGNT BRAV ISETuP VMEAV70 MATCH1U MATCrl1L MATCH4U OPCASDIS tTAGMATCH VCC IF VCC TAGMATCH IA10 BANKSEL MATCH1U M4TCH1L A10 BANKSEL MATCH2U MATCrl2L IA10 aAN SEL MATCH3U MATC 3L A10 BANKS L MATCrl4U MATCH4l IF VCC SETUP DPGNT CClUMN SETUP DPG T IF VCC OPCASD...

Page 97: ...138 22 159J 16uJ OR 135 40 178J 1836 0 18 s6 MMUCRMF 2L 184 3 187J QR 1e4 4C 224J CCNTSEL ROMTIM 8L 13 OR 270 15 270 22 270 40 2 1J 2 SJ 316J CACHCLR 7L 322 13 335J DTACK 9L 368 17 385J OR 322 40 362J OR 368 40 408J IF VCC PROG IFCD FC1 18 414 32 446J UDS 5L 414 9 423J 11 4 1840 0 414 7 1840J 421J IF ICC UIACK FCC 14 4 1837 0 460 6 C18 37 J C466J Fe1 18 460 32 4Y2J FC 2 19 460 34 494J LDS 1L 414 1...

Page 98: ...F VCe PR OG 1 1 11 40 0 1840 J IF VCG UIACK 14 1837 Q 1837J MMUORMF 2L 184 3 1t17J JR 1 40 224 CONTSEL RJMTIME 8L 13 OR 270 15 276 22 270 40 291J 2 J C31e CACHCLR 7L 322 13 335J JR 322 40 302J DTACK IL 3bb 17 385J CR 368 40 405J IFCD 4 4141 7 421 FC1 H 414 32 440 FCO FC1 4 18 460 6 400 32 466J 492J Fe 2 U JS SL 4141 9 423J 19 400 34 494J LDS 1L 414 1 415 CR 460 41 501 READ Co 414 10 424 APPENDIX B...

Page 99: ... IADRHIT VMEVF TA23 TA22 TA21 TA20 TA1 TA18 T 17 VMEVF NOGO ISX IOS NOVMEBUS MAS TA23 TA22 TA21 TA20 TA19 TA18 TA17 IAORHIT SX NOGO DS MAS TA23 TA22 TA21 TA20 TA19 TA1 TA17 IAORHIT SX NOGO DS MAS TA23 TA22 TA21 TA O TA19 TA18 TA17 IADRHIT SX NGGO DS MAS TA23 TA22 TA21 TA20 TA19 TA18 TA17 IADKHIT SX NOGO MAS IAORHIT SX VECT VMEVECT IF VCC CACHCLR MAS TA23 TA22 TA21 TA20 TA19 TA18 TA17 IAORHIT SX NO...

Page 100: ...V EVF TA23 TA22 TA21 TA20 TA19 TA18 TA17 VMEVF NCC O ISX IDS NCVMEBUS MAS TA23 TA22 TA21 TAZO TA19 TA18 TA17 IAORrlIT SX NOGO OS MAS TA23 TA22 TA21 TA20 TA19 TA18 TA17 IAORHIT Sx NOGC DS MAS TA23 TA22 TA21 TA20 TA19 TA18 TA17 IAORHIT SX NOGO DS MAS TA23 TA22 TA21 TA20 TA19 TA18 TA17 IAOR IT SX NOGO MASw IAGRHIT SX VECT VMEVECT IF Vce CACHCLR MAS TA23 TA22 TA21 TA20 iA19 TA18 TA17 IAORMIT SX NOGO O...

Page 101: ...C 14 SLAVECYC IF VCC SLAVECYC VOS DPGNT VDS SLAVECYC SLAVECYC 14 IF VCC OPCYON RESET lUSUTCK BUSE lERR IF VCC CLRO CACHCLR A01 RESET IF VCC CLR1 CACHCLR A02 RESET IF VCC 15 A01 A02 AS IRESET 15 IF Vce NOVECT 15 S RESET IRESET NGvECT DESCRIPTION MISCELLANEO S FUNCTIONS 108 APPENDIX B 3 C6 84 CKSM 5780 REV A M CROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www a...

Page 102: ...PORT MAP DECODER 128KBYTE ONSDARD RAM SET FOR VMESUS ADDRESSES Q 1FFFF PAL16L2 U28 HEET 8 PALDP21 MVME121 VME123 A23 A22 A21 A20 A19 A18 A17 LWORD IIACK GND AM1 AM3 AM2 AM4 15 IDPMATCH AMO AM5 VMEAV yce DPMATCH IA23 A22 A21 A20 A19 IACK LWORD VMEAV AM5 AM4 AM3 AM2 AM1 AMO IA23 A22 A21 A20 A19 IACK LWORD YMEAV AM5 AM4 AM3 AM2 AM1 AMO IA23 A22 A21 A2C A19 IACK LWDRD VMEAV AM5 AM4 AM3 AM2 AM1 AMO IA2...

Page 103: ...ASTIME RAM RT VUCASEN LCAS RAMwRT IF VCC UCAS ITA23 TA22 TA21 TA20 TA1 TA13 TA1 CK UDS CASTIME ITA23 TA22 TA21 TA20 TA19 iTA18 TA1 OK LDS CASTIME RAMWRT UCAS CASTH1E VUCASEN CASTIME VUCASEN UC AS VLCASEN CASTIME RAMWRT VLCASEN UCAS RAMWRT IF VCC RAMGO ITAZ3 TA22 TAZ1 TA20 TA19 TA1 TA17 UOS OK CASTH E ITA23 T 22 TAZ1 TA20 TA19 TA18 TA17 lOS OK c STIME DESCRIPTION RAM CAS S 128KBYTE ONB8ARJ DY AMIC ...

Page 104: ...TIME VLCASEN CASTIMc VLCASEN LCAS VUCASEN C STIME RAMwRT VUCASEN LCAS RAMWRT IF VCC UCAS ITA23 TA22 TA21 TA20 TA19 CK UCS CAS TH i ITA23 TA22 TA21 TA20 TA19 O LCS CASTI E RAMwRT LCAS CASTIME VUCASEN CASTIME VUCASEN UCAS VLCASEN CASTIME RAMwRT VLCASEN UCAS RAMWRT IF VCC RAMGC ITA23 T 22 TA21 TA20 TA19 UDS OK U STUe ITA23 TA22 TA21 TA20 TA1 i LOS CK C STI E DESCRIPTION RA CAS S S12K8VTE ONBOARD rVNA...

Page 105: ...2 A3 AO A1 A2 A3 I O A3 IA1 A3 IA2 A3 A4 AO A1 A2 A3 A4 IAO A4 IA1 A4 IA2 A4 IA3 A4 AS AO A1 A2 A3 A4 A5 IAO AS A1 A5 IA2 AS IA3 AS IA4 A5 A6 AO A1 A2 A3 A4 AS A6 IAO A6 IA1 A6 IA2 A6 IAS A6 IA4 A6 IA5 A6 A7 AO A1 A2 A3 A4 A5 A6 A7 IAO A7 IA1 A7 IA2 A7 IA3 A7 IA4 A7 AS A7 IA6 A7 DESCRIPTION RA REFRESrl COUNTER 112 MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOUR...

Page 106: ...EN LDS IF VCC S244EN UDS RcAO OVAS VWRITE SLAVECYC VDS VOTACK LCS REtlD OVAS S244E BUDS SZ44EN BLDS IF vec BUOS OV S UDS vaERR lvDTACK VMEAV READ OVAS UDS VBERR VDTACK VMEAV READ EN40 BUDS UDS IF vee oLDS OVAS LDS V5ERR VOTACK V EAV READ OVAS LDS VBERR VDTACK VMEAV READ E 4J BLOS LOS IF vec NoeBERR IV6ERR 18UOS 3LDS IF vce N06DTACK IVDTAC T IBuDS lOlDS IF veo RAMWRT IREAC vwRITE SLAVtCYC OEStRI TI...

Page 107: ...BORT IF VCC IPLl IE IRQ2 IRQ4 IRG5 IE IRQ3 IRG4 IRQ5 IE IRG6 IE MFPIRQ IE IRG7 IE ABORT IF vec IPL2 IE IRG4 IE IRG5 IE IRG6 IE MFPIRG IE IRG7 IE ABORT IF VCC MFPIACK A03 A02 A01 IACK ALTINT MFPIACK IACK IF VCC VPA IA01 A02 A03 IACK A01 A02 A03 IACK ABORT ALTINT IACK VMEVF IF VCC VMEVF A03 A02 A01 ABORT IACK ALTINT A03 A02 A01 IACK IEO ALTINT A03 A02 IACK ALTINT IA03 A02 IACK ALTINT IA03 A02 A01 IA...

Page 108: ...irect memory access double bus fault DTACK data transfer acknowledge DTR INDEX 41 5 9 23 29 39 7 17 29 30 37 5 7 39 40 41 44 53 17 33 35 42 45 52 54 55 52 53 55 30 37 101 21 22 29 45 46 45 51 54 29 30 31 49 19 41 43 97 19 29 30 36 38 39 44 46 47 53 54 44 24 52 53 55 30 39 28 29 30 37 42 46 4 7 14 16 27 37 43 44 36 33 34 36 43 33 35 33 36 29 31 33 34 36 16 40 43 21 22 39 17 3 30 45 46 96 26 37 44 4...

Page 109: ...ROM RS 232C 41 43 56 96 97 29 4 37 38 11 13 23 24 45 47 7 17 18 23 43 30 97 4 29 23 24 94 97 98 7 9 13 15 17 19 22 23 57 58 30 53 54 5 23 28 29 37 40 3 30 39 10 22 41 43 10 22 41 43 53 55 32 37 20 19 38 41 51 52 54 33 35 36 25 28 29 36 46 52 4 26 31 37 38 41 47 59 4 26 31 37 38 41 47 59 41 43 23 42 46 7 16 2 6 8 10 17 19 21 25 28 31 33 47 49 51 53 55 57 64 94 30 38 30 58 99 17 19 27 28 97 19 21 30...

Page 110: ...transition vector s VMEBERR VMEbus error VMEbus interface wait state WRITE write cycle 23 24 26 30 46 52 38 42 51 52 54 37 19 21 101 23 29 42 46 46 47 7 24 38 51 52 14 15 5 7 24 39 41 44 45 54 5 7 24 39 41 44 45 54 23 54 23 54 4 19 22 23 29 39 54 3 4 22 29 43 45 56 94 98 29 56 13 96 7 17 18 23 39 43 43 44 43 44 30 41 31 27 28 51 27 28 36 52 117 INDEX MICROSYSTEMS Artisan Technology Group Quality I...

Page 111: ... MOTOROLA INDEX 118 MICROSYSTEMS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 112: ...or a bus error occurs j The cache can be enabled disabled by software using the CACHEN bit in the MCR When the cache is disabled all cycles are cache ignore cycles k The cache can be frozen unfrozen by software using the FREEZE bit in the MCR The only effect of freezing the cache is that all cache validate cycles become cache ignore cycles Cache invalidate cycles are not affected Cache Flushing Th...

Page 113: ...__________________________ Please Print Name __________________ Title __________________ Company ________________ Division _______________ Street _________________ Mail Drop _____ Phone ________ City _________________ State __________ Zip _______ For Additional Motorola Publications Literature Distribution Center Four Phase Motorola Customer Support Tempe Operations 800 528 1908 616 West 24th Stre...

Page 114: ...ductor Products Inc p o BOX 20912 PHOENIX ARIZONA 85036 A SUBSIDIARY OF MOTOROLA INC 19108 PRINTED IN USA 7 85 MESSENGER 1500 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 115: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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