Motorola MTM700, Detailed Service Manual

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4.1 - 20 MTM700 Mobile Radio / Detailed Service Manual THEORY OF OPERATION (400 MHz)
The RedCap2 dual core (DSP / RISC) processor (U0100-1) located on the micro-controller sub-
board controls the radio hardware, communicates via various interfaces with external equipment or
accessories and performs digital signal processing. Beside its internal memory the RedCap2 uses
the FLASH Memory and the SRAM also located on the sub-board. The RedCap2 exchanges digi-
tized audio data with the CODEC via its Serial Audio Port (SAP). The RedCap2 sends digital base-
band data to the ADDAG and receives digital baseband data from the ABACUS via its Baseband
Port (BBP). To communicate with the RF IC's the RedCap2 uses its Queued Serial Peripheral Inter-
face A (QSPIA). A second interface, QSPIB is used for communication with external equipment or
accessories. The RedCap2 has 2 universal asynchronous receiver / transmitter ports (UARTA and
UARTB) for communication with external equipment e.g. a control head or a control terminal (PC).
UARTA communicates via SB9600 and RS232 protocol and UARTB communicates via SBEP proto-
col.
Host Memories
Flash Memory
The 4MByte FLASH Memory (U0102) located on the micro-controller sub-board contains the radio's
Application Software and the Radio Code Plug. The Code Plug stores customer related information
such as telephone numbers, addresses, etc. The RedCap2 accesses the data via a 22 bit wide
address bus (A0-A21), a 16 bit wide data bus (DQ0-DQ15), and 6 control lines (EN_CE, EN_OE,
EN_WE, EN_RP, EN_WP, VPP). When the FLASH Memory or the controller sub-board has been
replaced or the software needs to be upgraded, the new Code Plug and application software must
be programmed into the FLASH Memory.
SRAM Memory
The 512kByte SRAM (U0101) located on the micro controller sub-board stores data that can change
very frequently, and which is generated and stored by the Application Software during its normal
operation. The information is lost when the radio is turned off. The RedCap2 accesses the data via a
18 bit wide address bus (A0-A17), a 16 bit wide data bus (IO1-IO16), and 6 control lines (EN_CS,
EN_CS2, EN_OE, EN_WE, LB, UB).
Serial Peripheral Interface (SPI)
The RedCap2 uses the SPI protocol to communicate with the RF IC's ABACUS, ADDAG, LNODCT,
LVFRACN, ESCORT and PCIC. All these IC's are connected to the RedCap2's QSPIA module. The
interface comprises the lines SPIA_MOSI(TX), SPIA_MISO(RX), SPIA_CS, and SPIA_CLK. The
SPI bus is a synchronous bus, the timing clock signal CLK is sent while SPI data is transferred.
Therefore, whenever there is activity on either MOSI or MISO, there should be a uniform signal on
CLK.
The RedCap2 uses its module QSPIB to communicate with the DAC, the real time clock (RTC)
U0100, the optional RS232 interface connected to the 7 pin connector P0701, and the external
UART in the expansion head via the 40 pin connector J0500.
RS232, SB9600, SBEP Serial Interfaces
The RedCap2 uses three serial protocols to communicate with external devices: RS232, SB9600
and SBEP. The interface lines are available on the rear or front connectors, dependent on the inter-
face. Not all interfaces can be used at the same time.
SBEP Serial Interface
The RedCap2 communicates with the standard control head via the SBEP serial interface. This
interface comprises line BUS+ and is available on the 12 pin front connector J0550. Op-amps