Motorola MTM700, Detailed Service Manual

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THEORY OF OPERATION (400 MHz) MTM700 Mobile Radio / Detailed Service Manual 4.1 - 11
the image and half IF frequencies. From the output of the second pre-selector filter the received sig-
nal is sent to the RF input port of the first mixer.
Mixer
Mixer U5061 down-converts the incoming RF signal to the 73.35 MHz first IF, utilizing a first local
oscillator signal tuned 73.35 MHz below the desired receiver operating frequency. An impedance
matching network is placed between the mixer output and IF filter U5201.
IF Filter, Amplifier, AGC_2 Attenuator
The IF signal is routed via IF filter (U5201) to IF amplifier Q5201. From there it is routed either
through buffer Q5101 or through pin diode AGC attenuator (D5201, D5202) to IF IC U5101. The
AGC attenuator has two states (ON or OFF) and receives its control signal from the micro-proces-
sor.
IF Digitizing Subsystem
The IF Digitizing Subsystem is comprised of U5101. Here the IF signal is amplified and then mixed
with an internally generated 2nd LO signal to produce the second IF signal. The 2nd IF signal is first
processed by a variable gain amplifier and then converted to in-phase and quadrature (I and Q) dig-
ital data samples by means of a bandpass sigma-delta analog-to-digital converter. The I and Q dig-
ital signals are formatted into a single serial bit stream and sent for further processing to the Digital
Signal Processor (DSP) (part of micro-processor) over the Synchronous Serial Interface (SSI) data
link.
An internal AGC circuit controls the gain of the variable gain amplifier (VGA) to ensure that the max-
imum signal level into the ADC does not exceed a fixed analog ADC clip level and the rms output
level of the ADC is maintained at an established reference level.
An internal phase locked loop control circuit controls the frequency of voltage controlled oscillator
Q5180 which generates the 71.1 MHz 2
nd
LO injection frequency.
An internal phase locked loop control circuit controls the frequency of voltage controlled oscillator
Q5190 which generates the 18MHz sample clock frequency utilized by the ADC and decimation fil-
ters.
Both phase locked loops derive their frequency reference from the LVFRACN 16.8 MHz master
clock.