Motorola MPC860 PowerQUICC, User Manual

Page: 891 / 1106

MOTOROLA Chapter 34. Parallel I/O Ports 34-9
Part V. The Communications Processor Module
34.3.1 The Port B Registers
The four port B control registers determine whether a signal is open-drain, input or output,
and general-purpose or dedicated to a peripheral.
34.3.1.1 Port B Open-Drain Register (PBODR)
The port B open-drain register (PBODR) indicates when the port signals are conÞgured in
a normal or wired-OR conÞguration. Bits 14 and 15 of PBODR are not implemented.
PBODR is cleared by system reset.
1
Available for MPC860 Rev. B and later.
PB24 Port B24 SMRXD1 Ñ SMRXD1 = GND
PB23 Port B23 SMSYN1 SDACK1 SMSYN1 = GND
PB22 Port B22 SMSYN2 SDACK2 SMSYN2 = GND
PB21 Port B21 SMTXD2 L1CLKOB Ñ
PB20 Port B20 SMRXD2 L1CLKOA SMRXD2 = GND
PB19 Port B19 L1ST1 RTS1 Ñ
PB18 Port B18 L1ST2 RTS2 Ñ
PB17 Port B17 L1ST3 RTS3
1
/L1RQb Ñ
PB16 Port B16 L1ST4 RTS4
1
/L1RQa Ñ
PB15 Port B15 Ñ BRGO3 Ñ
PB14 Port B14 Ñ RSTRT1 Ñ
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ
Reset 0000_0000_0000_0000
R/W Ñ
Addr 0xAC0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field OD16 OD17 OD18 OD19 0D20 0D21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Addr 0xAC2
Figure 34-7. Port B Open-Drain Register (PBODR)
Table 34-6. Port B Pin Assignment (Continued)
Signal
Signal Function
PBPAR[DDn] = 0
PBPAR[DDn] = 1
Input to On-chip Peripherals
(Default)
PBDIR[DRn] = 0 PBDIR[DRn] = 1