Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 33. Parallel Interface Port 33-17
Part V. The Communications Processor Module
33.7.2.1 The BUSY Signal
In pulsed handshake mode, the PIP receiver can generate an additional BUSY handshake
signal that is useful when implementing a Centronics receiver interface. The BUSY output
is used to indicate a transfer in progress; the PIP receiver asserts BUSY as soon as data is
latched into the PIP data register. Figure 33-13 shows the pulsed handshake timing
including a BUSY signal.
Figure 33-13. Pulsed Handshake BUSY Signal
The timing of BUSY negation can be programmed relative to ACK; see Section 33.7.2.2,
ÒPulsed Handshake Timing.Ó Core software can also control the assertion and negation of
BUSY via PIPC; see Section 33.4.1, ÒPIP ConÞguration Register (PIPC).Ó
BUSY is multiplexed onto PB31. It can be used only with the 8-bit PIP interface (not the
16-bit interface). A PIP transmitter can be conÞgured to ignore BUSY or suspend assertion
of the STB output until the receiver BUSY signal is negated.
33.7.2.2 Pulsed Handshake Timing
When the PIP is under CP control, the pulsed-handshake timing parameters are governed
by PTPR[TPARn] Þelds, which deÞne an interval from 1 to 256 system clocks; see
Section 33.4.4, ÒPIP Timing Parameters Register (PTPR).Ó
Figure 33-14 shows how the timing parameter TPAR1 governs the setup time and TPAR2
deÞnes the pulse width of STB of a PIP transmitter using pulsed handshake mode timing.
Transmitter
Data
Transmitter
STBO
(STB)
Receiver
STBO
(ACK)
Receiver
PB31
(BUSY)
TSetup THold
TWidth