Motorola MPC860 PowerQUICC, User Manual

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33-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
33.4.3 PIP Mask Register
The PIP mask register (PIPM), whose layout is identical to PIPE, shares address 0xA9A
with the SMC2 mask register. Setting a PIPM bit enables the corresponding interrupt;
clearing a bit disables the interrupt. PIPM is cleared by reset.
33.4.4 PIP Timing Parameters Register (PTPR)
The PIP timing parameters register (PTPR) holds two timing parameters, TPAR1 and
TPAR2, used in the pulsed handshake modes for both sending and receiving. See
Section 33.7.2.2, ÒPulsed Handshake Timing.Ó
Table 33-8 describes PTPR Þelds.
33.4.5 The Port B Registers
The PIP uses parallel I/O port B. Figure 33-8 shows the basic operation of port B.
5 BSY Busy. Due to a lack of buffers, the PIP did not receive, and therefore discarded, a data byte/half-word.
6 RCH/
TCH Character received/transmitted. Indicates that a data character has been sent or received. Used to
generate interrupts to the core if the PIP is conÞgured to be controlled by core software.
7 RXB/
TXB Rx/Tx buffer. Under CP control, indicates that the PIP controller has closed the current buffer due to
one of the following events: the transfer byte count reaches zero (for Rx and Tx), a user-deÞned control
character is received and not rejected (R-bit = 0), or the programmable silence period times out.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field TPAR2 TPAR1
Reset 0
R/W R/W R/W
Addr 0xAB6
Figure 33-7. PIP Timing Parameters Register (PTPR)
Table 33-8. PTPR Field Descriptions
Bits Name Description
0Ð7 TPAR1 Timing parameter 1/2. DeÞnes the number of 860 general system clocks for TPAR1/TPAR2 in
transmitter or receiver pulsed handshake mode. The value 0x00 speciÞes one clock; 0xFF speciÞes
256 clocks. For a 25-MHz system, the general system clock period is 40 ns.
8Ð15 TPAR2
Table 33-7. PIPE Field Descriptions (Continued)
Bits Name Description