Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 28. SCC Ethernet Mode 28-19
Part V. The Communications Processor Module
28.17 Handling Errors in the Ethernet Controller
The Ethernet controller reports frame reception and transmission error conditions using
channel BDs, error counters, and SCCE. Table 28-4 describes transmission errors.
Table 28-4 describes reception errors.
28.18 Ethernet Mode Register (PSMR)
In Ethernet mode, the protocol-speciÞc mode register (PSMR), shown in Figure 28-7, is
used as the Ethernet mode register.
Table 28-4. Transmission Errors
Error Description
Transmitter underrun If this error occurs, the channel sends 32 bits that ensures a CRC error, stops sending the
buffer, closes it, sets the UN bit in the TxBD and SCCE[TXE]. The channel resumes
transmission after it receives a
RESTART TRANSMIT
command.
Carrier sense lost
during frame
transmission When this error occurs and no collision is found in the frame, the channel sets the CSL bit in
the TxBD, sets SCCE[TXE], and continues sending the buffer normally. No retries are
performed after this error occurs. Carrier sense is the logical OR of RENA and CLSN.
Retransmission
attempts limit expired The channel stops sending the buffer, closes it, sets the RL bit in the TxBD and SCCE[TXE].
The channel resumes transmission after it receives a
RESTART TRANSMIT
command.
Late collision When this error occurs, the channel stops sending the buffer, closes it, sets SCCE[TXE] and
the LC bit in the TxBD. The channel resumes transmission after it receives the
RESTART
TRANSMIT
command. This error is discussed further in the deÞnition of PSMR[LCW].
Heartbeat Some transceivers have a heartbeat (signal-quality error) self-test. To signify a good self-test,
the transceiver indicates a collision to the MPC860 within 20 clocks after the Ethernet
controller sends a frame. This heartbeat condition does not imply a collision error, but that the
transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the MPC860 does not
detect a heartbeat condition after sending a frame, a heartbeat error occurs; the channel
closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.
Table 28-5. Reception Errors
Error Description
Overrun The Ethernet controller maintains an internal FIFO for receiving data. When it overruns, the channel
writes the received byte over the previously received byte. The previous byte and frame status are lost.
The channel closes the buffer, sets RxBD[OV] and SCCE[RXF], and increments the discarded frame
counter (DISFC). The receiver then enters hunt mode.
Busy A frame was received and discarded because of a lack of buffers. The channel sets SCCE[BSY] and
increments DISFC. The receiver then enters hunt mode.
Non-Octet
Error
(Dribbling
Bits) The Ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet
aligned. It checks the CRC of the frame on the last octet boundary. If there is a CRC error, a frame
nonoctet aligned error is reported, SCCE[RXF] is set, and the alignment error counter is incremented. If
there is no CRC error, no error is reported. The receiver then enters hunt mode.
CRC When a CRC error occurs, the channel closes the buffer, sets SCCE[RXF] and CR in the RxBD, and
increments the CRC error counter (CRCEC). After receiving a frame with a CRC error, the receiver enters
hunt mode. CRC checking cannot be disabled, but CRC errors can be ignored if checking is not required.