Motorola MPC860 PowerQUICC, User Manual

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28-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
PSMR[SIP] is set and it is always in byte 3 of the last 32-bit write. The RxBD data length
does not include tag byte in the length calculation.
If system memory is 32 bits, the MPC860 32-bit write takes one bus cycle. If it is 16 or 8
bits, a 32-bit write takes two or four bus cycles. In any case, SDACK(1Ð2) are valid on each
bus cycle of a 32-bit write cycle and only during bus cycles associated with the Ethernet
receiver. As an alternate way to identify accesses from this SCC, a unique address type can
be chosen with the SDMA receive channel associated with the Ethernet controller.
Note that the tag byte is always written to byte 3 of the last SDMA write to the buffer and
is not necessarily appended to the last byte of the frame. The data length Þeld does not
include the tag byte. Also, SDACK(1Ð2) equal 0b00 whenever the frame is not a multiple
of four regardless of whether the tag byte is appended.
28.8 SCC Ethernet Parameter RAM
For Ethernet mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in
Table 28-1.
Table 28-1. SCC Ethernet Parameter RAM Memory Map
Offset
1
Name Width Description
0x30 C_PRES Word Preset CRC. For the 32-bit CRC-CCITT, initialize to 0xFFFFFFFF.
0x34 C_MASK Word Constant mask for CRC. For the 32-bit CRC-CCITT, initialized to 0xDEBB20E3.
0x38 CRCEC Word CRC error, alignment error, and discard frame counters. The CPM maintains these
32-bit (modulo 2
32
) counters that can be initialized while the channel is disabled.
CRCEC is incremented for each received frame with a CRC error, not including
frames not addressed to the controller, frames received in the out-of-buffers
condition, frames with overrun errors, or frames with alignment errors. ALEC is
incremented for frames received with dribbling bits, but does not include frames
not addressed to the controller, frames received in the out-of-buffers condition, or
frames with overrun errors. DISFC is incremented for frames discarded because of
the out-of-buffers condition or an overrun error. The CRC does not have to be
correct for DISFC to be incremented.
0x3C ALEC
0x40 DISFC
0x44 PADS Hword Short frame PAD character. Write the pad character pattern to be sent when short
frame padding is implemented into PADS. The pattern may be of any value, but
both the high and low bytes should be the same.
0x46 RET_LIM Hword Retry limit. Number of retries (typically 15 decimal) that can be made to send a
frame. An interrupt can be generated if the limit is reached.
0x48 RET_CNT Hword Retry limit counter. Temporary down-counter for counting retries.
0x4A MFLR Hword Maximum frame length register (Typically 1518 decimal). The Ethernet controller
checks the length of an incoming Ethernet frame against this limit. If it is exceeded,
the rest of the frame is discarded and LG is set in the last BD of that frame. The
controller reports frame status and length in the last BD. MFLR is defined as all
in-frame bytes between the start frame delimiter and the end of the frame.