21-28
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part V. The Communications Processor Module
21.2.5 IDL Bus Implementation
The full-duplex ISDN interchip digital link (IDL) interface connects a physical layer device
to the MPC860. The basic and primary rate of the IDL bus is supported by the MPC860. In
the basic rate, data on three channels (B1, B2, and D) is transferred in a 20-bit frame,
providing a full-duplex bandwidth of 160 Kbps. The MPC860 is an IDL slave device that
is clocked by the IDL bus master (physical layer device) and has separate receive and
transmit sections. Using both TDMs, the MPC860 supports two independent IDL buses as
shown in Figure 21-24.
Figure 21-24. Dual IDL Bus Application Example
21.2.5.1 ISDN Terminal Adaptor Application
An example IDL application is the ISDN terminal adaptor shown in Figure 21-25. In such
an application, the IDL interface connects the 2B+D channels between the MPC860,
CODEC, and S/T transceiver. An SCC is conÞgured in HDLC mode to handle the D
channel. Another SCC is used to rate adapt the terminal data stream over the Þrst B channel.
This SCC is conÞgured for HDLC mode if V.120 rate adaptation is required. The second B
channel is then routed to the CODEC as a digital voice channel, if preferred. The SPI is used
to send initialization commands and periodically check status from the S/T transceiver. The
SMC connected to the terminal is conÞgured for UART.
S/T
S/T
U
U
S/T
S/T
IDL1
S/T
Interfaces
IDL2
ISDN TE
NT
U
Interfaces
MPC860
Summary of Contents for MPC860 PowerQUICC
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