Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-3
Part V. The Communications Processor Module
To minimize the latency associated with slower, character-oriented protocols, an SDMA
writes each character to memory as it arrives without waiting for the next character, and
always reads using 16-bit half-word transfers. A transfer may take multiple bus cycles if the
memory provides a less than 32-bit port size. An SDMA uses back-to-back bus cycles for
the entire transferÑ4-word bursts, 32-bit reads, and 8-, 16-, or 32-bit writesÑbefore
relinquishing the bus. For example, an SDMA channel reading a 32-bit word from a 16-bit
memory takes two consecutive bus cycles.
An SDMA steals cycles with no arbitration overhead unless an external device is bus
master. Figure 20-2 shows an SDMA stealing a cycle from an internal bus master.
Figure 20-2. SDMA U-Bus Arbitration (Cycle Steal)
20.2 SDMA Registers
All SDMA channels share one conÞguration register (SDCR), a status register (SDSR), a
mask register (SDMR), and a read-only, address register (SDAR). The conÞguration of
each serial controller also affects their dedicated SDMA channelsÕ behavior. The following
sub-sections describe the SDMA registers.
20.2.1 SDMA ConÞguration Register (SDCR)
The SDMA conÞguration register (SDCR) conÞgures all 16 virtual SDMA channels. It
controls the channelsÕ U-bus priority level and freeze-signal (FRZ) behavior. It is always
read/write in supervisor mode, even though writing to the SDCR is not recommended
unless the CPM is disabled. Figure 20-3 shows the register format.
CLK
TS
TA
SDMA Internally
Requests the Bus
Other Cycle SDMA Cycle Other Cycle