Motorola MPC860 PowerQUICC, User Manual

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20-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
20.1.1 SDMA Transfers
Each SDMA channel can be programmed to output a 3-bit function code that identiÞes the
channel currently accessing memory. The SDMA channel can implement true little-endian,
PowerPC little-endian, or big-endian byte ordering when accessing buffers. These features
are programmed in the receive and transmit function code registers associated with each
serial controller and within an IDMA channelÕs BD; see Section 20.3.4, ÒIDMA Buffer
Descriptors (BD).Ó
If a bus error occurs when the SDMA conducts an access, the CP generates a unique
interrupt in the SDMA status register (SDSR). The interrupt service routine reads the
SDMA address register (SDAR) to determine the address that the bus error occurred on.
The individual channel that caused the bus error can be found by reading the Rx and Tx
internal data pointers from the protocol-speciÞc parameter RAM of the serial controllers.
If an SDMA bus error occurs, all CPM activity ceases and the entire CPM must be reset in
the CPM command register (CPCR); see Section 19.5.2, ÒCP Command Register (CPCR).Ó
20.1.2 U-Bus Arbitration and the SDMA Channels
The SDMA channels, I-cache, D-cache, and SIU all contend for the U-bus as internal
masters with their relative priorities determined by an arbitration ID. The user can adjust
the SDMA bus arbitration priority, but the other internal masters have Þxed arbitration IDs;
see Section 20.2.1, ÒSDMA ConÞguration Register (SDCR).Ó All 16 virtual SDMA
channels share the same arbitration ID, and thus have the same priority relative to the other
internal masters. See Table 20-1.
Once an SDMA channel obtains the external system bus, it remains master for the whole
transactionÑa byte, half-word, word or burst transferÑbefore relinquishing the bus. This
feature, in combination with the zero-clock arbitration overhead provided by the U-bus,
increases bus efÞciency and lowers latency.
Table 20-1. U-Bus Arbitration IDs
Arbitration Level Unit
7 (highest priority) Ñ
6 SDMA (SDCR[RAID]=0b00)
5 SDMA (SDCR[RAID]=0b01)
4 D-cache
3 I-cache
2 SDMA (SDCR[RAID]=0b10)
1 SDMA (SDCR[RAID]=0b11)
0 PowerPC Core
Note: DRAM refresh normally has a U-bus arbitration level of -1 (lowest). If, however, four refresh
periods expire without servicing, the arbitration level is promoted to 6.5.
TIMERS