Motorola MPC860 PowerQUICC, User Manual

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19-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
The speciÞc deÞnition of each controllersÕ parameter RAM is protocol dependent and is
described in the individual protocol chapters.
19.7 The RISC Timer Table
The CP can control a maximum of 16 timers separate and distinct from the four
general-purpose timers and baud-rate generators of the CPM. The RISC timer table free the
core from scanning a software timer table and are used for protocols that do not require
extreme precision. The timers are clocked from an internal timer accessible to the CP only.
Each pair of timers can be conÞgured as a pulse width modulation (PWM) channel; a
maximum of eight channels are supportable. The output of the channel is driven on one of
the port B pins.
The following list summarizes the main features of the RISC timer table:
¥ Supports up to 16 timers
¥ Supports up to 8 PWM channels
¥ Three timer modes: one-shot, restart, and PWM
¥ Maskable interrupt on timer expiration
¥ Programmable timer resolutions as low as 41
m
s at 25 MHz
¥ Maximum timeout periods of 172 seconds at 25 MHz
¥ Continuously updated reference counter
RISC timer table operations are based on a ÒtickÓ in the CP internal timer that is
programmed in the RCCR; see Section 19.5.1, ÒRISC Controller ConÞguration Register
(RCCR).Ó The tick is a multiple of 1,024 general system clocks. The RISC timer table has
the lowest priority of all CP operations, so if it is busy with other tasks and unable to service
the timer during a tick interval, one or more of the timers might not be updated. This
behavior can be used to estimate the worst-case loading of the CP; see Section 19.7.8,
ÒUsing the RISC Timers to Track CP Loading.Ó The timer table is conÞgured using the
RCCR, the timer table parameter RAM, and the RISC controller timer event/mask registers
(RTER/RTMR), and by issuing
SET TIMER
to the CPCR.
19.7.1 RISC Timer Table Scan Algorithm
The CP scans the timer table once every tick of the internal CP timer. For each valid timer
in the table, the CP decrements the count and checks for a timeout. If no timeout occurs, it
moves to the next timer. If a timeout does occur, the CP sets the corresponding event bit in
RTER and then checks R_TMR to see if the timer must be restarted. If it does, the CP leaves
the timer valid bit set in the R_TMV register and resets the current count to the initial count;
otherwise, the CP clears R_TMV. Once the timer table is scanned, the CP updates
TM_CNT and stops working on the timer table until the next scan tick.
If
SET TIMER
is issued, the CP makes the appropriate modiÞcations to the timer table and
parameter RAM, but does not scan the timer table until the next tick of the internal CP