MOTOROLA
Chapter 16. Memory Controller
16-23
Part IV. Hardware Interface
Figure 16-22. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1)
When TRLX and CSNT are set in a write-memory access, the strobe line, WE is negated
one clock earlier than in the normal case. If ACS
¹
0, CS is also negated one clock earlier,
as shown in Figure 16-23 and Figure 16-24. When a bank is selected to operate with
external transfer acknowledge (SETA and TRLX = 1), the memory controller does not
support external devices that provide TA to complete the transfer with zero wait states. The
minimum access duration in this case is 3 clock cycles.
Clock
Address
TS
TA
CS
R/W
WE
OE
Data
ACS = 10
ACS = 11
Summary of Contents for MPC860 PowerQUICC
Page 3: ...MPC860UM AD 07 98 REV 1 MPC860 PowerQUICC ª UserÕs Manual ...
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Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
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Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
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Page 632: ...21 44 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...
Page 660: ...22 28 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...
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Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...
Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
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