Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 14. MPC860 External Bus Interface 14-25
Part IV. Hardware Interface
Table 14-2 lists the bytes required on the data bus for read cycles.
Ñ denotes a byte not required during that read cycle.
Table 14-3 lists data transfer patterns for write cycles when the MPC860 initiates accesses.
Ñ denotes a byte not required during that read cycle.
14.4.6 Arbitration Phase
The external bus design provides for a single bus master at any one time, either the MPC860
or an external device. One or more external bus devices can have the capability of becoming
bus master for the external bus. Bus arbitration may be handled either by an external central
bus arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for
one external bus master besides the MPC860. The arbitration conÞguration (external or
internal) is set at system reset. See Section 16.8, ÒExternal Master Support.Ó.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. A
device needing the bus asserts BR, and then waits for the arbiter to assert BG. The new
Table 14-2. Data Bus Requirements For Read Cycles
Transfer
Size
TSIZ[0Ð1]
Address 32-Bit Port 16-Bit Port 8-Bit Port
A30 A31 D[0Ð7] D[8Ð15] D[16ÐD3] D[24Ð31] D[0Ð7] D[8Ð15] D[0Ð7]
Byte 0 1 0 0 OP0 Ñ Ñ Ñ OP0 Ñ OP0
0 1 0 1 Ñ OP1 Ñ Ñ Ñ OP1 OP1
0 1 1 0 Ñ Ñ OP2 Ñ OP2 Ñ OP2
0 1 1 1 Ñ Ñ Ñ OP3 Ñ OP3 OP3
Half-Word 1 0 0 0 OP0 OP1 Ñ Ñ OP0 OP1 OP0
1 0 1 0 Ñ Ñ OP2 OP3 OP2 OP3 OP2
Word 0 0 0 0 OP0 OP1 OP2 OP3 OP0 OP1 OP0
Table 14-3. Data Bus Contents for Write Cycles
Transfer
Size
TSIZE
Address External Data Bus Pattern
A30 A31 D[0Ð7] D[8Ð15] D[16ÐD3] D[24Ð31]
Byte 0 1 0 0 OP0 Ñ Ñ Ñ
0 1 0 1 OP1 OP1 Ñ Ñ
0 1 1 0 OP2 Ñ OP2 Ñ
0 1 1 1 OP3 OP3 Ñ OP3
Half-Word 1 0 0 0 OP0 OP1 Ñ Ñ
1 0 1 0 OP2 OP3 OP2 OP3
Word 0 0 0 0 OP0 OP1 OP2 OP3