Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 11. System Interface Unit 11-21
Part III. Configuration
the bus monitor terminates the cycle by internally asserting TEA. The programmability of
the timeout allows for a variation in system peripheral response time. The timing
mechanism is clocked by the system clock divided by eight. The maximum value is 2,040
system clocks. The bus monitor is always active when FRZ is asserted or when a debug
mode request is pending, regardless of the state of the SYPCR[BME] bit.
Note that if the bus monitor is disabled, transfer errors do not cause TEA to be asserted.
11.7 The Software Watchdog Timer
The SIU provides the software watchdog timer (SWT) option that prevents system lockup
when software gets trapped in loops without a controlled exit. The software watchdog timer
is enabled after HRESET to automatically generate a HRESET if it times out. If the
software watchdog timer is unneeded, clear SYPCR[SWE] to disable it. If it is used, the
software watchdog timer requires a special service sequence to be executed periodically;
otherwise, the watchdog timer times out and issues a reset or an NMI, which is programmed
by SYPCR[SWRI]. Once SYPCR is written by the software, SYPCR[SWE] cannot be
changed. See Section 11.4.3, ÒSystem Protection Control Register (SYPCR).Ó To service
the software watchdog timer, follow these steps:
1. Write 0x556C to the software service register. (SWSR)
2. Write 0xAA39 to the SWSR.
This sequence clears the watchdog timer and the timing process repeats. If a value other
than 0x556C or 0xAA39 is used, the entire sequence must start over. Although the writes
must occur in the correct order before a timeout occurs, any number of instructions may be
executed between the writes. This allows interrupts and exceptions to occur between the
two writes when necessary. See Figure 11-15.
Figure 11-15. Software Watchdog Timer Service State Diagram
The decrementer begins counting when it is loaded with a value from the SWTC Þeld. This
value is then loaded into a 16-bit down-counter clocked by the system clock. When
necessary, an additional divide by 2,048 prescaler is used. After the timer reaches 0x0, a
software watchdog expiration request is issued to the reset or NMI control logic. At reset,
State 0
Waiting for 0x556C
State 1
Waiting for 0xAA39
Reset
Not 0xAA39/DonÕt_Reload
0xAA39/Reload
0x556C/DonÕt_Reload
Not 0x556C/DonÕt_Reload