Motorola MPC860 PowerQUICC, User Manual

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8-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
performed as a critical-word-Þrst operation; the critical word is simultaneously written to
the cache and forwarded to the requesting unit, thus minimizing stalls due to cache Þll
latency. Both caches provide storage for cache tags and perform cache block replacement
(LRU) function.
Both caches are tightly coupled to the MPC860Õs system interface unit (SIU) to allow
efÞcient access to the system memory controller and other bus masters. The SIU receives
requests for bus operations from the instruction and data caches, and executes the
operations per the external bus protocol.
The data cache provides buffers for load and store bus operations. The data cache supplies
data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU is directly
coupled to the data cache to allow efÞcient movement of data to and from the
general-purpose registers. The load/store unit provides all logic required to calculate
effective addresses, handles data alignment to and from the data cache, and provides
sequencing for load and store string and multiple operations. Write operations to the data
cache can be performed on a byte, half-word, or word basis.
The instruction cache provides a 32-bit interface to the instruction sequencer. The
instruction sequencer uses the instruction cache as much as possible in order to sustain the
high throughput provided by the four-entry instruction queue.
8.1 Instruction Cache Organization
The MPC860 instruction cache is organized as 128 sets of two blocks, as shown in
Figure 8-1. Each block consists of 16 bytes, a single state bit, a lock bit, and an address tag.