Motorola MPC821FADS User Manual Download Page 36

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Signal Descriptions

5-22

MPC821FADS-DB USER’S MANUAL

MOTOROLA

108

MODIN

O, X

Mode Clock In signal. This signal selects the

4MHz clock generator or the 32768Hz crystal

as clock sources for the MPC821. Its is driven

by the DS2/4 signal.

109

GND

—

110

BBVD1

O, X

Buffered Battery Voltage Detect 1 signal for

PCMCIA slot A. IP_A6 on the MPC821. Used

in conjunction with BBVD2 to determine the

battery status of a PC card.

111

GND

—

112

BCD2

O, L

Buffered Card Detect 2 signal for PCMCIA slot

A. IP_A3 on the MPC823. Used as a card

detect indication in conjunction with BCD1.

113

GND

—

114

BBVD2

O, X

Buffered Battery Voltage Detect 2 signal

PCMCIA slot A. IP_A5 on the MPC821. Used

in conjunction with BBVD1 to determine the

battery status of a PC card.

115

GND

—

116

117

—

Not connected.

118

DP0

I/O

Data Parity line 0. DP0/IRQ3 on the MPC821.

This signal can generate and receive parity

data for the D[0:7] signals that are connected to

the DRAM SIMM. It may not be configured as

IRQ3.

119

V3.3

—

120

DP2

I/O

Data Parity line 2. DP2/IRQ5 on the MPC821.

This signal can generate and receive parity

data for the D[16:23] signals that are

connected to the DRAM SIMM. It may not be

configured as IRQ5.

121

V3.3

—

122

DP1

I/O

Data Parity line1. DP1/IRQ4 on the MPC821.

This signal can generate and receive parity

data for the D[8:15] signals that are connected

to the DRAM SIMM. It may not be configured

as IRQ4.

123

V3.3

—

124

—

Not connected.

125

V3.3

—

126

IRQ1

I/O, L

Interrupt Request line 1.Pulled up, but

otherwise unused on this board.

127

V3.3

—

128

SPARE3

I/O, X

Spare line 3. Pulled up, but otherwise unused

on this board.

129

V3.3

—

Table 5-10. PM2 Interconnect Signals (Continued)

PIN

MOTHERBOARD

SIGNAL

DAUGHTERBOARD

SIGNAL

INPUT/

OUTPUT

DESCRIPTION

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

Summary of Contents for MPC821FADS

Page 1: ...ical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiar...

Page 2: ...nse from IBM I2C is a registered tradmeark of Philips Corporation All other trademarks are the property of their respective owners Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 3: ...he MPC8xxFADS while those on the component side are to serve hardware expansion via a dedicated adaptor Also a set of logic analyzer connectors is featured matching the new high density HP16500 logic analyzer adaptors to provide fast connection to a logic analyzer while saving board space and reducing EMI 1 1 TERMINOLOGY ADI Application Development Interface ADS Application Development System BCSR...

Page 4: ...ed Oscillator with a 3 5MHz Frequency Range On Board Expansion Connectors Including All MPC821 Pins and MPC8xxFADS Control and Status Signals Onboard High Density Logic Analyzer Connectors That Support Fast Connection to HP16500 Logic Analyzer MPC821 Modem Tool Support Table 1 1 MPC821FADS Daughterboard Specifications CHARACTERISTICS SPECIFICATIONS Microprocessor MPC821 50MHz Operating temperature...

Page 5: ...ROLA MPC821FADS DB USER S MANUAL 1 3 Figure 1 1 MPC821FADS Daughterboard Block Diagram MPC821 CLOCKS DAUGHTER EXPANSION CONNECTORS EXPANSION CONNECTORS EXPANSION CONNECTORS BOARD ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 6: ...the board for your design 2 1 CONFIGURING THE BOARD Before you configure the MPC821FADS daughterboard you may have to change the jumpers settings before you can install the board into your system Since they are factory set and tested they may not be set correctly for your particular configuration Figure 2 1 illustrates the location of these jumpers LEDs and connectors on the board The MPC821FADS d...

Page 7: ...Installation 2 2 MPC821FADS DB USER S MANUAL MOTOROLA Figure 2 1 MPC821FADS Daughterboard Parts Locator Top Side HALO ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 8: ... with 3 3V output only can be used with a 14 pin form factor while 3 3V oscillators can be used with an 8 pin form factor Inserting a 14 pin form factor 3 3V clock generator into U1 could cause permanent damage to your device Since the MPC821 clock input is not 5V tolerant any clock generator inserted into U1 must have a 3 3V compatible output If you insert a 5V output clock generator into U1 you ...

Page 9: ...ons 2 and 3 a power on reset is generated from the main 3 3V power rail In other words when the 3 3V power rail gets below 2 805V a power on reset is generated 2 1 3 Selecting the Keep Alive Power Source The J2 jumper is used to select the keep alive power source When the J2 jumper is between positions 1 and 2 the keep alive power is fed from the main 3 3V bus When you need to connect an external ...

Page 10: ... the MPC821 s internal logic When the J3 jumper is between positions 1 and 2 VDDL is supplied with 3 3V of power When the J3 jumper is between positions 2 and 3 VDDL is supplied with 2 2V of power The J3 jumper is factory set between positions 1 and 2 Figure 2 5 VDDL Source 1 1 3 3V VDDL 2V VDDL J3 J3 ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 11: ...3 3V power bus is receiving power from the MPC8xxFADS motherboard 3 1 3 Memory Map The memory map is the same on all daughterboards See Section 3 3 Memory Map of the MPC8xxFADS User s Manual for more information 3 1 4 Programming the MPC821 Registers To program the MPC821 registers see Section 3 1 7 Programming the MPC821 Registers of the MPC8xxFADS User s Manual Warning The onboard GND bridges ph...

Page 12: ...reset During a keep alive power on or when there is a voltage drop of that input into the above range a power on reset is generated the PORESET input of the MPC821 is asserted for approximately 4 seconds When you select the main power source a dedicated voltage detector made by Seiko S 8052ANY NH X with a detection voltage range of 2 595 2 805V generates the power on reset During a main 3 3V bus p...

Page 13: ...S User s Manual for details 4 2 INTERRUPTS The only external interrupt that is applied to the MPC821 via its interrupt controller is the abort NMI interrupt which is generated by a push button and logic that resides on the motherboard 4 3 CLOCK GENERATOR Although most of the clock generator logic is found on the daughterboard it is explained in detail in the motherboard manual since it is common t...

Page 14: ...ontrol and status register BCSR control signals and some of the status signals are available on the motherboard connectors and on the expansion connectors The BCSRs control most of the functions available on the MPC821FADS daughterboard and the MPC8xxFADS motherboard ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 15: ...erboard uses the following connectors to interconnect with external devices P1 P2 P3 P4 P5 P6 and P8 Logic analyzer connectors PM1 PM2 PM3 and PM4 Motherboard connectors PX1 PX2 PX3 and PX4 Expansion connectors P7 LCD panel connector MPC8xxFADS s P8 Serial port expansion connector1 1 This connector is located on the motherboard It is documented here since its contents depends on the daughterboard ...

Page 16: ...8xxFADS User s Manual Table 5 1 P1 Interconnect Signals PIN MOTHER BOARD SIGNAL DAUGHTER BOARD SIGNAL PIN MOTHER BOARD SIGNAL DAUGHTER BOARD SIGNAL 1 2 3 GND GND 4 5 TS TS 6 TA TA 7 TS TS 8 TA TA 9 F_CS F_CS 10 VFLS0 VFLS0 11 BCSRCS BCSRCS 12 VFLS1 VFLS1 13 DRMCS1 DRMCS1 14 AT0 AT0 15 DRMCS2 DRMCS2 16 AT1 AT1 17 SDRMCS SDRMCS 18 AT2 AT2 19 CS5 CS5 20 AT3 AT3 21 CS6 CS6 22 VF0 VF0 23 CS7 CS7 24 VF1...

Page 17: ...1A CE1A 10 BS1A BS1A 11 CE2A CE2A 12 BS2A BS2A 13 BWAITA BWAITA 14 BS3A BS3A 15 BB BB 16 WE0 WE0 17 BR BR 18 WE1 WE1 19 BWP BWP 20 WE2 WE2 21 BCD2 BCD2 22 WE3 WE3 23 BCD1 BCD1 24 DRM_W DRM_W 25 BG BG 26 EDOOE EDOOE 27 BI BI 28 GPL2 GPL2 29 BRDY BRDY 30 GPL3 GPL3 31 BADDR28 BADDR28 32 GPL4A GPL4A 33 BADDR29 BADDR29 34 GPL4B GPL4B 35 BADDR30 BADDR30 36 GPL5A GPL5A 37 AS AS 38 GPL5B GPL5B NOTE Not Co...

Page 18: ...4 5 TEA TEA 6 7 A0 A0 8 A16 A16 9 A1 A1 10 A17 A17 11 A2 A2 12 A18 A18 13 A3 A3 14 A19 A19 15 A4 A4 16 A20 A20 17 A5 A5 18 A21 A21 19 A6 A6 20 A22 A22 21 A7 A7 22 A23 A23 23 A8 A8 24 A24 A24 25 A9 A9 26 A25 A25 27 A10 A10 28 A26 A26 29 A11 A11 30 A27 A27 31 A12 A12 32 A28 A28 33 A13 A13 34 A29 A29 35 A14 A14 36 A30 A30 37 A15 A15 38 A31 A31 NOTE Not Connected ARCHIVED BY FREESCALE SEM ICONDUCTOR I...

Page 19: ...1 PA1 10 LD7 PD14 11 PA2 PA2 12 LD6 PD13 13 PA3 PA3 14 LD5 PD12 15 PA4 PA4 16 LD4 PD11 17 PA5 PA5 18 LD3 PD10 19 PA6 PA6 20 LD2 PD9 21 PA7 PA7 22 LD1 PD8 23 PA8 PA8 24 LD0 PD7 25 PA9 PA9 26 LOE PD6 27 PA10 PA10 28 VSYNC PD5 29 PA11 PA11 30 HSYNC PD4 31 IRDTXD IRDTXD 32 SHIFT_C PD3 33 IRDRXD IRDRXD 34 SPARE1 SPARE1 35 ETHTX ETHTX 36 SPARE2 SPARE2 37 ETHRXS ETHRXS 38 SPARE3 SPARE3 NOTE Not Connected...

Page 20: ... USBVCC0 10 DSCK DSCK 11 VDOEXTCK 12 DSDO DSDO 13 USBSPD 14 TMS TMS 15 VDORST 16 TRST TRST 17 BVS1 BVS1 18 NMI NMI 19 BVS2 BVS2 20 IRQ1 IRQ1 21 BBVD1 BBVD1 22 IRQ2 IRQ2 23 BBVD2 BBVD2 24 IRQ3 IRQ3 25 RSTCNF RSTCNF 26 FRZ FRZ 27 TEXP TEXP 28 BINPAK BINPAK 29 HRESET HRESET 30 DP0 DP0 31 SRESET SRESET 32 DP1 DP1 33 PORST PORST 34 DP2 DP2 35 R_PORI R_PORI 36 DP3 DP3 37 IRQ7 IRQ7 38 V3 3 NOTE Not Conne...

Page 21: ...B15 10 PB30 PB30 11 PB16 PB16 12 PB31 PB31 13 PB17 PB17 14 PC4 PC4 15 PB18 PB18 16 PC5 PC5 17 E_TENA E_TENA 18 PC6 PC6 19 RSRXD2 RSRXD2 20 PC7 PC7 21 RSTXD2 RSTXD2 22 PC8 PC8 23 RSDTR2 RSDTR2 24 PC9 PC9 25 RSDTR1 RSDTR1 26 E_RENA E_RENA 27 RSRXD1 RSRXD1 28 E_CLSN E_CLSN 29 RSTXD1 RSTXD1 30 PC12 PC12 31 PB26 PB26 32 PC13 PC13 33 PB27 PB27 34 PC14 PC14 35 PB28 PB28 36 SPARE4 SPARE4 37 PB29 PB29 38 N...

Page 22: ...GND 4 5 6 7 D0 D0 8 D16 D16 9 D1 D1 10 D17 D17 11 D2 D2 12 D18 D18 13 D3 D3 14 D19 D19 15 D4 D4 16 D20 D20 17 D5 D5 18 D21 D21 19 D6 D6 20 D22 D22 21 D7 D7 22 D23 D23 23 D8 D8 24 D24 D24 25 D9 D9 26 D25 D25 27 D10 D10 28 D26 D26 29 D11 D11 30 D27 D27 31 D12 D12 32 D28 D28 33 D13 D13 34 D29 D29 35 D14 D14 36 D30 D30 37 D15 D15 38 D31 D31 NOTE Not Connected ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 23: ...INPUT OUTPUT DESCRIPTION 1 SHIFT_C I O LCD Shift Clock 2 GND 3 4 5 LOE I O LCD Output Enable for TFT displays or passive panels LCD_AC signal 6 GND 7 HSYNC I O Horizontal Sync signal Displays line beginning mark 8 GND 9 VSYNC I O Vertical Sync signal Displays new frame beginning mark 10 GND 11 12 13 LD0 I O LCD Data line 0 14 GND 15 LD1 I O LCD Data line 1 16 GND 17 LD2 I O LCD Data line 2 18 GND ...

Page 24: ...30 GND 31 Pin is cut to allow 30 pin connector insertion 32 33 34 35 I O 36 VCC O 5V supply 37 I O 38 VCC O 5V supply 39 I O 40 VCC O 5V supply NOTE I Input and O Output Table 5 8 P7 Interconnect Signals Continued PIN SIGNAL INPUT OUTPUT DESCRIPTION ARCHIVED BY FREESCALE SEM ICONDUCTOR INC ...

Page 25: ...ors manufactured by Molex These connectors are arranged in a square shape so that there is a short route to the PCB As shown in Figure 5 1 the connectors are set asymmetrically to prevent incorrect daughterboard insertion Figure 5 1 Motherboard Connectors Mechanical Assembly Top Side 1 1 1 1 PM1 PM4 PM2 PM3 17 49mm 11 14mm 30 19mm 93 98mm 71 12mm 46 3mm 13 68mm ARCHIVED BY FREESCALE SEM ICONDUCTOR...

Page 26: ... I O L Burst signal Pulled up but otherwise unused on this board 10 VCC VCC 11 GPL4A GPL4A X L General Purpose Line 4 of UPMA Not used on this board 12 VCC VCC 13 TA TA I O L Transfer Acknowledge signal Indicates the end of a bus cycle Used with MPC8xxFADS logic 14 VCC VCC 15 TS TS I O L Transfer Start signal Pulled up but otherwise unused on this board 16 VCC VCC 17 GPL5B GPL5B O L General Purpos...

Page 27: ...s chip select for the Flash SIMM Pulled up When the flash is disabled via the BCSR this signal can be used off board via the daughterboard s expansion connectors 38 GND GND 39 CS6 CS6 Chip Select line 6 Unused on this board 40 GND GND 41 CE2A CE2A I L Card Enable 2 signal for PCMCIA Slot A Enables the odd address bytes Used by on board PCMCIA port 42 GND GND 43 DRMCS2 DRMCS2 I O L DRAM Chip Select...

Page 28: ...M Write Enable 1 or PCMCIA I O Write signal Used to qualify write cycles to the flash memory and as I O write for the PCMCIA channel 58 GND GND 59 BS2A BS2A I L Byte Select 2 signal for UPMA Selects offset two bytes within a word Used for DRAM access 60 GND GND 61 WE0 WE0 I L GPCM Write Enable 0 or PCMCIA I O Read signal Used to qualify write cycles to the flash memory and as I O reads from the PC...

Page 29: ... board 76 GND GND 77 REG_A REG_A I TS L Register Select Port A signal TSIZ0 REG on the MPC821 Used with the PCMCIA port to select attribute memory or I O space 78 GND GND 79 A30 A30 I TS Address line 30 80 GND GND 81 A21 A21 I TS Address line 21 82 GND GND 83 A20 A20 I TS Address line 20 84 GND GND 85 A7 A7 I TS Address line 7 86 GND GND 87 A15 A15 I TS Address line 15 88 GND GND 89 A14 A14 I TS A...

Page 30: ... GND GND 115 A27 A27 I TS Address line 27 116 GND GND 117 A28 A28 I TS Address line 28 118 GND GND 119 A26 A26 I TS Address line 26 120 GND GND 121 A25 A25 I TS Address line 25 122 GND GND 123 A24 A24 I TS Address line 24 124 GND GND 125 A22 A22 I TS Address line 22 126 GND GND 127 A3 A3 I TS Address line 3 Not used on this board 128 GND GND 129 A23 A23 I TS Address line 23 130 GND GND 131 A4 A4 I...

Page 31: ...ata Input Used on the MPC8xxFADS as a debug port serial data driven by the debug port controller If the ADI bundle is not connected to the MPC8xxFADS this signal can be driven by the external debug JTAG port controller 8 GND GND 9 10 DSCK DSCK I O Debug Port Serial Clock input or JTAG Port Serial Clock input Used on the MPC8xxFADS as a debug port serial clock driven by the debug port controller If...

Page 32: ... IRQ2 I O L Interrupt Request line 2 Pulled up but otherwise unused on this board 27 GND GND 28 29 30 AT3 AT3 I O Address Type 3 signal IP_B7 PTR AT3 on the MPC821 31 GND GND 32 SPARE4 SPARE4 I O Spare line 4 Pulled up but otherwise unused on this board 33 GND GND 34 VFLS0 VFLS0 I O Visible History Flushes Status 0 signal IP_B0 IWP0 VFLS0 on the MPC821 This signal can be configured for another fun...

Page 33: ...uffers Output Enable signal The OP1 signal of the PCMCIA interface Enables address buffers towards the PC card 49 GND GND 50 51 52 BADDR30 BADDR30 I O X Burst Address line 30 Dedicated for external master support Used to generate a burst address during external master burst cycles Pulled up but otherwise unused on this board 53 GND GND 54 ALE_A ALE_A I H Address Latch Enable signal for PCMCIA Slot...

Page 34: ...GND 72 MODCK2 MODCK2 I O Mode Clock 2 signal OP3 MODCK2 DSDO on the MPC821 Used at power on reset as MODCK2 and configured afterwards as OP3 This signal can be configured for another function 73 GND GND 74 75 76 Not connected 77 GND GND 78 79 80 SRESET SRESET I O L OD Soft Reset signal This signal is driven by onboard logic and may be driven by offboard logic with open drain gate only 81 GND GND 8...

Page 35: ...tage Sense 1 signal for PCMCIA slot A IP_A0 on the MPC821 Used in conjunction with BVS2 to determine the operation voltage of a PCMCIA card 97 GND GND 98 BRDY BRDY O H Buffered Ready signal for PCMCIA slot A IP_A7 on the MPC821 Used as PCMCIA port A card ready indication 99 GND GND 100 101 102 DP3 DP3 I O X Data Parity line 3 DP3 IRQ6 on the MPC821 This signal can generate and receive parity data ...

Page 36: ... O Data Parity line 0 DP0 IRQ3 on the MPC821 This signal can generate and receive parity data for the D 0 7 signals that are connected to the DRAM SIMM It may not be configured as IRQ3 119 V3 3 V3 3 120 DP2 DP2 I O Data Parity line 2 DP2 IRQ5 on the MPC821 This signal can generate and receive parity data for the D 16 23 signals that are connected to the DRAM SIMM It may not be configured as IRQ5 1...

Page 37: ...ignals PIN MOTHERBOARD SIGNAL DAUGHTERBOARD SIGNAL INPUT OUTPUT DESCRIPTION 1 ETHRX ETHRX O X Ethernet Port Receive Data signal When the Ethernet port is disabled via the BCSR1 it is three stated This signal also appears at P8 2 GND GND 3 4 UUFEN UUFEN O L Not used on this board 5 ETHTX ETHTX I X Ethernet Port Transmit Data signal Also appears at P8 6 GND GND 7 8 PC9 PC9 X X Port C Bit 9 Also appe...

Page 38: ... When the Ethernet port is disabled via the BCSR1 this signal is three stated Also appears at P8 28 GND GND 29 ETHRCK ETHRCK O X Ethernet Port Receive Clock signal When the Ethernet port is disabled via the BCSR1 this signal is three stated Also appears at P8 30 GND GND 31 32 USBSPD O X Unused on this board 33 PB31 PB31 I O X Port B Bit 31 Also appears at P8 but is otherwise unused 34 BINPAK BINPA...

Page 39: ... 2 is disabled via the BCSR1 this signal is three stated and can be used for another function Also appears at P8 44 RSDTR2 RSDTR2 O L RS 232 Port 2 DTR signal When the RS 232 port 2 is disabled via the BCSR1 this signal is three stated and can be used for another function Also appears at P8 45 PC14 PC14 I O X Port C Bit 14 Also appears at P8 but is otherwise unused 46 GND GND 47 Not connected 48 G...

Page 40: ... PA3 PA3 I O X Port A Bit 3 Also appears at P8 but is otherwise unused 72 GND GND 73 74 PA2 PA2 I O X Port A Bit 2 Also appears at P8 but is otherwise unused 75 PB17 PB17 I O X Port B Bit 17 Also appears at P8 but is otherwise unused 76 PB18 PB18 I O X Port B Bit 18 Also appears at P8 but is otherwise unused 77 E_TENA E_TENA I O H Ethernet Port Transmit Enable signal It is connected to the serial ...

Page 41: ... Bit 14 Also appears at P8 but is otherwise unused 98 PC4 PC4 I O X Port C Bit 4 Also appears at P8 but is otherwise unused 99 PC5 PC5 I O X Port C Bit 5 Also appears at P8 but is otherwise unused 100 PC6 PC6 I O X Port C Bit 6 Also appears at P8 but is otherwise unused 101 GND GND 102 RS_EN2 RS_EN2 O L RS 232 Port 2 Enable signal It is connected to the BCSR1 103 SHIFT_C SHIFT_C I O X Shift Clock ...

Page 42: ...therboard Also appears at P8 and a dedicated LCD connector 118 LD5 LD5 I O LCD Data line 5 PD12 LD5 on the MPC821 Not used on the MPC8xxFADS motherboard Also appears at P8 and a dedicated LCD connector 119 LD6 LD6 I O X LCD Data line 6 PD13 LD6 on the MPC821 Not used on the MPC8xxFADS motherboard Also appears at P8 and a dedicated LCD connector 120 LD7 LD7 I O X LCD Data line 7 PD14 LD7 on the MPC...

Page 43: ...Interconnect Signals PIN MOTHERBOARD SIGNAL DAUGHTERBOARD SIGNAL INPUT OUTPUT DESCRIPTION 1 GND GND 2 D31 D31 I O X Data line 31 3 GND GND 4 D30 D30 I O X Data line 30 5 GND GND 6 D29 D29 I O X Data line 29 7 GND GND 8 D28 D28 I O X Data line 28 9 GND GND 10 11 12 D27 D27 I O X Data line 27 13 GND GND 14 D26 D26 I O X Data line 26 Table 5 11 PM3 Interconnect Signals Continued PIN MOTHERBOARD SIGNA...

Page 44: ...a line 20 29 GND GND 30 31 32 D19 D19 I O X Data line 19 33 GND GND 34 D18 D18 I O X Data line 18 35 GND GND 36 D17 D17 I O X Data line 17 37 GND GND 38 D16 D16 I O X Data line 16 39 GND GND 40 41 42 D15 D15 I O X Data line 15 43 GND GND 44 D14 D14 I O X Data line 14 45 GND GND 46 D13 D13 I O X Data line 13 47 GND GND 48 D12 D12 I O X Data line 12 Table 5 12 PM4 Interconnect Signals Continued PIN ...

Page 45: ...Data line 6 65 GND GND 66 D5 D5 I O X Data line 5 67 GND GND 68 D4 D4 I O X Data line 4 69 GND GND 70 71 72 D3 D3 I O X Data line 3 73 GND GND 74 D2 D2 I O X Data line 2 75 GND GND 76 D1 D1 I O X Data line 1 77 GND GND 78 D0 D0 I O X Data line 0 79 GND GND 80 81 DRMH_W DRMH_W O L DRAM Half Word signal Sets the DRAM to 16 bit data bus width Table 5 12 PM4 Interconnect Signals Continued PIN MOTHERBO...

Page 46: ...rboard revision code 94 EXTOLI1 EXTOLI1 I O X External Tool Identification 1 signal Connected to the BCSR2 95 DBREV2 DBREV2 I X Daughterboard Revision Code 2 signal The LSB of the daughterboard revision code 96 EXTOLI3 EXTOLI3 I O X External Tool Identification 3 signal Connected to the BCSR2 97 BCSR3R1 BCSR3R1 I O X Board Control and Status Register 3 Reserved 1 signal It is the reserved signal 1...

Page 47: ...ignal is active low MPC8xxFADS logic notices that the evaluated MPC821 resides in its socket If inactive either the MPC821 is out of socket or a daughterboard is not connected in which case the MPC8xxFADS becomes a debugging station 108 GND GND 109 110 Not connected 111 112 GND GND 113 114 Not connected 115 116 GND GND 117 118 Not connected 119 120 GND GND 121 122 Not connected 123 124 GND GND 125...

Page 48: ...entical in signal assignment to the motherboard connectors However there is a difference between PM3 and PX3 which is a result of the 134 Not connected 135 136 GND GND 137 138 Not connected 139 140 GND GND NOTE I Input O Output L Low and X Don t Care Figure 5 2 Expansion Connectors Mechanical Assembly Table 5 12 PM4 Interconnect Signals Continued PIN MOTHERBOARD SIGNAL DAUGHTERBOARD SIGNAL INPUT O...

Page 49: ... PIN SIGNAL ATTRIBUTE DESCRIPTION No Difference Figure 5 3 PX2 PM2 Interconnect Signal Differences PIN SIGNAL ATTRIBUTE DESCRIPTION 76 EXTCLK O X External Clock 4MHz clock generator output the input clock to the MPC NOTE O Output and X Don t Care Figure 5 4 PX3 PM3 Interconnect Signal Differences PIN SIGNAL ATTRIBUTE DESCRIPTION No Difference Figure 5 5 PX4 PM4 Interconnect Signal Differences PIN ...

Page 50: ...DA Port Transmit Data signal See PM3 5 11 42 A5 LD4 I O LCD Data line 4 signal See PM3 117 A6 LD3 I O LCD Data line 3 signal See PM3 116 A7 LD2 I O LCD Data line 2 signal See PM3 115 A8 LD1 I O LCD Data line 1 signal See PM3 114 A9 ETHTCK I O Ethernet Port Transmit Clock signal See PM3 27 A10 ETHRCK I O Ethernet Port Receive Clock signal See PM3 29 A11 Not connected A12 PA4 I O Port A Bit 4 BRGCLK...

Page 51: ...dy 2 signal See PM3 44 B11 RSTXD2 I O RS 232 Transmit Data 2 signal See PM3 5 11 42 B12 RSRXD2 I O RS 232 Reveive Data 2 signal See PM3 43 B13 E_TENA I O Ethernet Transmit Enable signal See PM3 77 B14 PB19 I O Port B Bit 19 See PM3 76 B15 PB17 I O Port B Bit 17 See PM3 75 B16 PB16 I O Port B Bit 16 See PM3 93 B17 Not connected B18 Not connected B19 GND B20 BINPAK I O Buffered INPAK signal See PM3 ...

Page 52: ... 121 C16 LD7 I O LCD Data line 7 See PM3 120 C17 LD6 I O LCD Data line 6 See PM3 119 C18 LD5 I O LCD Data line 5 See PM3 118 C19 LD0 I O LCD Data line 0 signal See PM3 113 C20 LOE I O LCD Output Enable signal See PM3 110 C21 VCC C22 HRESET I O L Hard Reset signal See PM2 84 C23 SRESET I O L Soft Reset signal See PM2 80 C24 Not connected C25 VCC C26 SHIFT_C I O Shift Clock signal See PM3 103 C27 VP...

Page 53: ...SMD 023 00027 3 C13 Capacitor 100µF 10V 10 Size D Tantalum SMD 023 00038 1 C30 C35 Capacitor 1µF 25V 10 Size A Tantalum SMD 023 00028 2 C18 C21 Capacitor 10pF 50V 10 COG 1206 Ceramic SMD 021 00097 2 C26 Capacitor 5000pF 50V 10 1206 Ceramic SMD 021 00080 1 C27 Capacitor 0 68µF 20V 10 Size A Tantalum SMD 023 00041 1 D1 Diode SMD LL4004G SMD 048 LL4004G 1 H1 H2 H3 Gnd Bridge Gold Plated TH 022 00011 ...

Page 54: ... Resistor Network 75 Ω 5 Eight Resistors 16 Pin SMD 051 00060 3 RN4 Resistor Network 4 7K 5 Eight Resistors 14 Pin SMD 051 00036 1 T1S MMDF3N03HD Transistor TMOS Dual 3A SMD 051 MMDF3N03HD 1 U1 4 MHz Clock Generator 3 3V CMOS Levels TH 048 00072 1 U1 Socket 14 Pin PC Socket TH 009 00135 1 U2 MPC821 19 x 19 357 Pin BGA TH 009 00284 1 U2 Socket 361 Pin 19 x 19 BGA ZIF Socket TH 009 00284 1 U6 74LCX0...

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