MOTOROLA
Chapter 3. Receiver
3-3
Receiver Interface Signals
3.2
Receiver Interface Signals
This section describes the interface signals of the MC92603 receiver. Each signal’s name,
function, direction, and active state is described in Table 3-1. The table’s signal names use
the letter ‘x’ as a place holder for the link identifier letter ‘A’ through ‘D.’ Internal signals
listed in the table are not available at the external interface of the device, but are presented
to help illustrate the device’s operation.
Table 3-1. MC92603 Receiver Interface Signals
Signal Name
Description
Function
Direction
Active
State
RECV_x_[7:0]
Received byte
Receive data bits 7 through 0
Output
—
RECV_x_DV
Data valid indicator
If TBIE is high, this is the receive data, bit 8.
If TBIE is low, this is data valid indicator.
Output
—
RECV_x_K
Special data indicator
If TBIE is high, this indicates that receiver has
detected an error. The type of error is indicated
in the data byte (RECV_x_7–RECV_x_0).
If TBIE is low, this indicates whether the 8-bit
receive data is a ‘special’ code group.
Output
—
RECV_x_COMMA
COMMA indicator
This is the COMMA DETECT indicator.
RECV_x_ERR
Receiver error
If TBIE is high, this is receive data, bit 9.
If TBIE is low, see Table 3-10 and Table 3-15.
Output
—
RECV_x_RCLK
Receiver clock
Internally generated clock synchronized with
receiver data. If TBIE is high, then this clock
frequency is half of the data frequency.
Output
—
RECV_x_RCLK_B
Receiver clock
complement
If TBIE is high, this is the complement of
RECV_x_RCLK.
If TBIE is low, this signal is low.
Output
—
XCVR_x_DISABLE
Transceiver disable
When active receiver is disabled
Input
High
XMIT_x_K
Transmitter/receiver input If TBIE is high, XMIT_x_K enables automatic
realignment on COMMA code groups. If
XMIT_x_K is low, initial alignment on COMMAs
occurs but subsequent realignments are
disabled.
If TBIE is low, this signal is used by the
transmitter logic and ignored by the receiver
logic.
Input
—
JPACK
Enable Jumbo frames
When high, this signal increases the depth of the
receive FIFO allowing longer packets of data
between bytes that may be repeated or dropped
to prevent overruns or underruns. Only needed if
RCCE is low (reference clock mode).
Input
High
RECV_REF_A
Receiver A clock enable
If RECV_REF_A and RCCE are high, then data
will be synchronized to Channel A’s recovered
clock.
Input
High
WSYNC1 &
WSYNC0
Word synchronization
modes
If either input is high, then all enabled receivers
are being used in unison to receive
synchronized data.
Input
High
BSYNC
Byte alignment mode
Indicates that byte alignment is required. If it is
low, no byte alignment is done.
Input
—
Summary of Contents for MC92603
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