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Motorola MC68340, User Manual

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Summary of Contents for MC68340

Page 1: ...MC68340UM AD Rev 1 INTEGRATED PROCESSOR WITHDMA USER S MANUAL MOTOROLA ...

Page 2: ...r any other application in which the fajlure 01 the MolDrola produd could create a situation where peraonal Injury or death may occur Should Buyer purchase or use MolDrola products lor any sudl unintended or unauthorized application Buyer ahaJIindemnify and hold MolOroIa and ita ollicars employees subsidiaries affiliates and distributors harmless against ali dalms costa damages and expenses and re...

Page 3: ...1 8593 Timer Modules IEEE 1149 1 Test Access Port Applications Electrical Characteristics Ordering Information and Mechanical Data The Motorola High End Technical Publication Department provides a FAX number for you to submit any questions and comments about this document We welcome your suggestions for improving our documentation or any questions concerning our products Please provide the part nu...

Page 4: ...and Protection 1 6 Clock Synthesizer 1 6 Chip Select and Wait State Generation 1 6 Interrupt Handling 1 6 Discrete 1 0 Pins 1 6 IEEE 1149 1 Test Access Port 1 7 Direct Memory Access Module 1 7 Serial Module 1 7 Timer Modules 1 8 Power Consumption Management 1 8 Physical 1 9 Compact Disc Interactive 1 9 More Information 1 1 0 Section 2 Signal Descriptions 2 1 Signal Index 2 2 2 2 Address Bus 2 4 2 ...

Page 5: ...10 4 Clock Mode Select MODCK 2 9 2 11 Instrumentation and Emulation Signals 2 9 2 11 1 Instruction Fetch IFETCH 2 9 2 11 2 Instruction Pipe IPIPE 2 9 2 11 3 Breakpoint BKPT 2 10 2 11 4 Freeze FREEZE 2 1 0 2 12 DMA Module Signals 2 10 2 12 1 DMA Request DREQ2 DREQ1 2 10 2 12 2 DMA Acknowledge DACK2 DACK1 2 1 0 2 12 3 DMA Done DONE2 DONE1 2 10 2 13 Serial Module Signals 2 11 2 13 1 Serial Crystal Os...

Page 6: ...Bus A31 AO 3 4 Address Strobe AS 3 4 Data Bus 015 00 3 4 Data Strobe OS 3 4 Bus Cycle Termination Signals 3 4 Data Transfer and Size Acknowledge Signals OSACK1 and OSACKO 3 4 Bus Error BERR 3 5 Autovector AVEC 3 5 Data Transfer Mechanism 3 5 Dynamic Bus Sizing 3 5 Misaligned Operands 3 7 Operand Transfer Cases 3 7 Byte Operand to 8 Bit Port Odd or Even AO X 3 7 Byte Operand to 16 Bit Port Even AO ...

Page 7: ...ry Operation 3 36 Halt Operation 3 38 Double Bus Fault 3 39 Bus Arbitration 3 40 Bus Request 3 43 Bus Grant 3 43 Bus Grant Acknowledge 3 43 Bus Arbitration Control 3 44 Show Cycles 3 44 Reset Operation 3 46 Section 4 System Integration Module Module Overview 4 1 Module Operation 4 2 Module Base Address Register Operation 4 2 System Configuration and Protection Operation 4 3 System Configuration 4 ...

Page 8: ...Register SYPCR 4 24 Periodic Interrupt Control Register PICR 4 26 Periodic Interrupt Timer Register PITR 4 27 Software Service Register SWSR 4 28 Clock Synthesizer Control Register SYNCR 4 28 Chip Select Registers 4 29 Base Address Registers 4 30 Address Mask Registers 4 31 Chip Select Registers Programming Example 4 33 External Bus Interface ControL 4 33 Port A Pin Assignment Register 1 PPARA1 4 ...

Page 9: ...11 Table lookup and Interpolation TBl 5 12 Unimplemented Instructions 5 12 Instruction Format and Notation 5 12 Instruction Summary 5 15 Condition Code Register 5 20 Data Movement Instructions 5 21 Integer Arithmetic Operations 5 22 logic Instructions 5 24 Shift and Rotate Instructions 5 24 Bit Manipulation Instructions 5 25 Binary Coded Decimal BCD Instructions 5 26 Program Control Instructions 5...

Page 10: ...5 48 Illegal or Unimplemented Instructions 5 48 Privilege Violations 5 49 Tracing 5 50 Interrupts 5 51 Retum from Exception 5 52 Fault Recovery 5 53 Types of Faults 5 55 Type I Released Write Faults 5 55 Type II Prefetch Operand RMW and MOVEP Faults 5 56 Type III Faults During MOVEM Operand Transfer 5 57 Type IV Faults During Exception Processing 5 57 Correcting a Fault 5 57 Type Completing Releas...

Page 11: ...eturn Program Counter RPC 5 67 Current Instruction Program Counter PCC 5 67 Returning from BDM 5 68 Serial Interlace 5 68 CPU Serial Logic 5 69 Development System Serial Logic 5 71 Command Set 5 73 Command Format 5 73 Command Sequence Diagram 5 74 Command Set Summary 5 75 Read AID Register RAREG RDREG 5 76 Write AID Register WAREGIWDREG 5 77 Read System Register RSREG 5 77 Write System Register WS...

Page 12: ... 3 Negative Tails 5 96 Instruction Timing Tables 5 97 Fetch Effective Address 5 99 Calculate Effective Address 5 1 00 MOVE Instruction 5 1 01 Special Purpose MOVE Instruction 5 1 01 Arithmetic Logic Instructions 5 102 Immediate Arithmetic Logic Instructions 5 1 05 Binary Coded Decimal and Extended Instructions 5 1 06 Single Operand Instructions 5 107 Shift Rotate Instructions 5 108 Bit Manipulatio...

Page 13: ... 6 20 Channel Termination 6 20 Interrupt Operation 6 20 Fast Termination Option 6 20 Register Description 6 22 Module Configuration Register MCR 6 23 Interrupt Register INTR 6 26 Channel Control Register CCR 6 26 Channel Status Register CSR 6 30 Function Code Register FCR 6 32 Source Address Register SAR 6 33 Destination Address Register DAR 6 33 Byte Transfer Counter Register BTC 6 34 Data Packin...

Page 14: ...6 Channel B Transmitter Serial Data Output TxDB 7 6 Channel B Receiver Serial Data Input RxDB 7 6 Channel A Request To Send RTSA 7 6 RTSA 7 6 OPO 7 6 Channel B Request To Send RTSB 7 6 RTSB 7 7 OP1 7 7 Channel A Clear To Send CTSA 7 7 Channel B Clear To Send CTSB 7 7 Channel A Transmitter Ready TxRDYA 7 7 TxRDYA 7 7 OP6 7 7 Channel A Receiver Ready RxRDYA 7 7 RxRDYA 7 7 FFULLA 7 7 OP4 7 7 Operatio...

Page 15: ...t Status Register ISR 7 32 Interrupt Enable Register IER 7 34 Input Port IP 7 35 Output Port Control Register OPCR 7 35 Output Port Data Register OP 7 37 Mode Register 2 MR2 7 37 Programming 7 40 Serial Module Initialization 7 40 VO Driver Example 7 40 Interrupt Handling 7 40 Serial Module Initialization Sequence 7 46 Serial Module Configuration 7 46 Serial Module Example Configuration Code 7 47 S...

Page 16: ...Register IR 8 20 Control Register CR 8 20 Status Register SR 8 23 Counter Register CNTR 8 25 Preload 1 Register PREL1 8 25 Preload 2 Register PREL2 8 26 Compare Register COM 8 26 Timer Module Initialization Sequence 8 27 Timer Module Configuration 8 27 Timer Module Example Configuration Code 8 28 Section 9 IEEE 1149 1 Test Access Port 9 1 Overview 9 1 9 2 TAP Controller 9 2 9 3 Boundary Scan Regis...

Page 17: ...er Reduction at 5V 10 11 MC68340V 3 3 V 10 13 Section 11 Electrical Characteristics Maximum Rating 11 1 Thermal Characteristics 11 1 Power Considerations 11 2 AC Electrical Specification Definitions 11 2 DC Electrical Specifications 11 5 AC Electrical Specifications Control Timing 11 6 AC Timing Specifications 11 8 DMA Module AC Electrical Specifications 11 19 Timer Module Electrical Specification...

Page 18: ...dge Cycle Timing Exception Signaled 3 26 3 14 Interrupt Acknowledge Cycle Flowchart 3 28 3 15 Interrupt Acknowledge Cycle Timing 3 29 3 16 Autovector Operation Timing 3 31 3 17 Bus Error without DSACKx 3 35 3 18 Late Bus Error with DSACKx 3 36 3 19 Retry Sequence 3 37 3 20 Late Retry Sequence 3 38 3 21 HALT Timing 3 39 3 22 Bus Arbitration Flowchart for Single Request 3 41 3 23 Bus Arbitration Tim...

Page 19: ...Stack for Prefetches and Operands 5 62 5 16 Format C BERR Stack on MOVEM Operand 5 62 5 17 Format C Four and Six Word BERRStack 5 63 5 18 In Circuit Emulator Configuration 5 64 5 19 Bus State Analyzer Configuration 5 64 5 20 BDM Block Diagram 5 65 5 21 BDM Command Execution Flowchart 5 68 5 22 Debug Serial 1 0 Block Diagram 5 70 5 23 Serial Interface Timing Diagram 5 71 5 24 BKPT Timing for Single...

Page 20: ...g Model 6 23 6 16 Packing and Unpacking of Operands 6 35 7 1 Simplified Block Diagram 7 1 7 2 External and Internal Interface Signals 7 5 7 3 Baud Rate Generator Block Diagram 7 8 7 4 Transmitter and Receiver Functional Diagram 7 9 7 5 Transmitter Timing Diagram 7 10 7 6 Receiver Timing Diagram 7 12 7 7 Looping Modes Functional Diagram 7 15 7 8 Multidrop Mode Timing Diagram 7 16 7 9 Serial Module ...

Page 21: ...between Two Outputs 10 9 10 14 Circuitry for Interfacing 8 Bit Device to 16 Bit Memory in Single Address DMA Mode 10 10 10 15 MC68340 Current vs Activity at 5 V 10 11 10 16 MC68340 Current vs Voltageffemperature 10 12 10 17 MC68340 Current vs Clock Frequency at 5 V 10 12 11 1 Drive Levels and Test Points for AC Specifications 11 4 11 2 Read Cycle Timing Diagram 11 11 11 3 Write Cycle Timing Diagra...

Page 22: ...OCle Timing Xl 1 l 11 17 Serial Module Asynchronous Mode Timing SCLK 16X 11 23 11 18 Serial Module Synchronous Mode Timing Diagram 11 23 11 19 Test Clock Input Timing Diagram 11 25 11 20 Boundary Scan Timing Diagram 11 26 11 21 Test Access Port Timing Diagram 11 26 MOTOROLA MC68340 USER S MANUAL xxi ...

Page 23: ...Register 4 16 4 6 SHENx Control Bits 4 22 4 7 Deriving Software Watchdog Timeout 4 25 4 8 BMTx Encoding 4 26 4 9 PIRQL Encoding 4 26 4 10 DDx Encoding 4 32 4 11 PSx Encoding 4 32 5 1 Instruction Set 5 6 5 2 Instruction Set Summary 5 16 5 3 Condition Code Computations 5 20 5 4 Data Movement Operations 5 21 5 5 Integer Arithmetic Operations 5 23 5 6 Logic Operations 5 24 5 7 Shift and Rotate Operati...

Page 24: ...ding 6 29 6 5 BBx Encoding and Bus Bandwidth 6 29 6 6 Address Space Encoding 6 32 7 1 FRZx Control Bits 7 20 7 2 PMx and PT Control Bits 7 23 7 3 B Cx Control Bits 7 24 7 4 RCSx Control Bits 7 26 7 5 TCSx Control Bits 7 27 7 6 MISCx Control Bits 7 28 7 7 TCx Control Bits 7 29 7 8 RCx Control Bits 7 30 7 9 CMx Control Bits 7 38 7 10 SBx Control Bits 7 39 8 1 OCx Encoding 8 17 8 2 FRZx Control Bits ...

Page 25: ...xxiv MC68340 USER S MANUAL MOTOROLA ...

Page 26: ...s high level of functional integration results in significant reductions in component count power consumption board space and cost while yielding much higher system reliability and shorter design time The 3 3 V MC68340V is particularly attractive to applications requiring a very tight power budget Complete code compatibility with the MC68000 and MC68010 affords the designer access to a broad base ...

Page 27: ...ally Relegated to External PAls TTL and ASIC such as System Configuration System Protection Chip Select and Wait State Generation Clock Generation External Bus Interface Periodic Interrupt Timer Interrupt Response Bus Arbitration Dynamic Bus Sizing IEEE 1149 1 Boundary Scan JTAG Up to 16 Discrete 1 0 Lines Power On Reset 32 Address Lines 16 Data Lines Power Consumption Control Static HCMOS Technol...

Page 28: ...me power consumption cost board space pin count and programming The equivalent functionality can easily require 20 separate components Each component might have 16 64 pins totaling over 350 connections Most of these connections require interconnects or are duplications Each connection is a candidate for a bad solder jOint or misrouted trace Each component is another part to qualify purchase invent...

Page 29: ...lications Many addressing modes complement these instructions including predecrement and postincrement which allow simple stack and queue maintenance and scaled indexed for efficient table accesses Data types and addreSSing modes are supported orthogonally by all data operations and with all appropriate addressing modes Position independent code is easily written The CPU32 is specially optimized t...

Page 30: ...DMA control line Modules and their registers are accessed in the memory map of the CPU32 and DMA for easy access by general M68000 instructions and are relocatable Each module may be assigned its own interrupt level response vector and arbitration priority Since each module is a self contained design and adheres to the 1MB interface speCifications the modules may appear on other M68300 family prod...

Page 31: ...s possible to completely stop the system clock without losing the contents of the internal registers 1 3 1 4 CHIP SELECT AND WAIT STATE GENERATION Four programmable chip selects provide signals to enable external memory and peripheral circuits providing all handshaking and timing signals with up to 175 ns access times with a 25 MHz system clock 265 ns 16 78 MHz Each chip select signal has an assoc...

Page 32: ...e external logic The source and destination port size can be selected independently when they are different the data will be packed or unpacked An 8 bit disk interface can be read twice before the concatenated 16 bit result is passed into memory Byte word and long word counts up to 32 bits can be transferred All addresses and transfer counters are 32 bits Addresses increment or remain constant as ...

Page 33: ... counter timers as well as a simple timer in the SIM40 These general purpose counterltimers can be used for preCisely timed events without the errors to which software based counters and timers are susceptible e g errors caused by dynamic memory refreshing DMA cycle steals and interrupt servicing The programmable timer operating modes are input capture output compare square wave generation variabl...

Page 34: ... the chip including the clock oscillator A 144 pins are used for signals and power The MC68340 is available in a gull wing ceramic quad flat pack CQFP with 25 6 mil 0 001 in lead spacing or a 15 x 15 plastic pin grid array PPGA with 0 1 in pin spacing 1 6 COMPACT DISC INTERACTIVE The MC68340 was designed to meet the needs of many markets including compact disc interactive CD I CD I is an emerging ...

Page 35: ...MC68340P D MC68340 Product Brief MC68340UM AD MC68340 User s Manual M68000PM AD M68000 Family Programmer s Reference Manual AN1063 D DRAM Controller for the MC68340 AN453 Software Implementation of SPI on the MC68340 BR5731D M68340 Evaluation System Product Brief BR7291D The 68K Source BR1407 D 3 3 Volt Logic and Interface Circuits 1 10 MC68340 USER S MANUAL MOTOROLA ...

Page 36: ...BG BGACK RMC IR06IPORT B6 IR05lPORT B5 IR03lPORT B3 CS3IIR04 pORT B4 CS2llR02JPORT B2 CS1 IR01 pORT B1 CSO AVEC MODCK f ORT so MOTOROLA SYSTEM INTEGRATION MODULE CPU32 CORE TWO CHANNEL DMA CONTROLLER 1MB gzo uz I l IUiI I I 0 _ 0 0 C G IOCOo TWO CHANNEL SERiAl I O OUTPUT PORT TIMER TIMER MODULE MODULE Figure 2 1 Functional Signal Groups MC68340 USER S MANUAL RxDA TxDA CTSA RxDB TxDB CTSB TxRDYNOP6...

Page 37: ...s complete and the Out MCS8340 has relinquished the bus Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus In mastership Data and Size DSACK1 Provides asynchronous data transfers and dynamic bus In Acknowledge DSACKO sizing Read Modify Write Cycle RMC Identifies the bus cycle as part of an indivisible read Out modify write operation Address Strobe AS Indicates that a val...

Page 38: ...erial Crystal Oscillator X1 X2 Connections for an external crystal to the serial module internal oscillator circuit Serial Clock SCLK External serial module clock input In Transmitter ReadylOP6 TxRDYA Indicates transmit buffer has a character or becomes a OutlOut parallel output Receiver Readyl RxRDYA Indicates receive buffer has a character the receiver OuVOutlOut FIFO FulVOP4 FIFO buffer is full...

Page 39: ...be programmed as the most significant eight address bits pqrt A parallel I O or interrupt acknowledge signals These pins can be used for more than one of their multiplexed functions as long as the external demultiplexing circuit properly resolves interaction between the different functions A31 A24 These pins can function as the most significant eight address bits Port A7 AO These eight pins can se...

Page 40: ... Bits 3 2 1 0 Address Spaces 0 0 0 0 Reserved Motorola 0 0 0 1 User Data Space 0 0 1 0 User Program Space 0 0 1 1 Reserved User 0 1 0 0 Reserved Motorola 0 1 0 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 0 1 1 1 CPU Space 1 x x x DMA Space 2 5 CHIP SELECTS CS3 CSO These pins can be programmed to be chip select output signals port 8 parallel I O and autovector input or additional inter...

Page 41: ...and Size Acknowledge DSACK1 DSACKO These two active low input signals allow asynchronous data transfers and dynamic data bus sizing between the MC68340 and external devices as listed in Table 2 3 During bus cycles external devices assert DSACK1 and or DSACKO as part of the bus protocol During a read cycle this signals the MC68340 to terminate the bus cycle and to latch the data During a write cycl...

Page 42: ... 1 1 Three Byte 0 0 Long Word 2 7 5 ReadlWrite RIW This active high output signal is driven by the bus master to indicate the direction of a data transfer on the bus A logic one indicates a read from a slave device a logic zero indicates a write to a slave device 2 8 BUS ARBITRATION SIGNALS The following signals are the bus arbitration control signals used to determine the bus master Refer to Sect...

Page 43: ...or a description of bus reset operation and Section 5 CPU32 for information about the reset exception 2 9 2 Halt HAL1 This active low open drain bidirectional signal is asserted to suspend external bus activity to request a retry when used with BERR or to perform a single step operation As an output HALT indicates a double bus fault by the CPU32 Refer to Section 3 Bus Operation for a description o...

Page 44: ...lator VCO furnishes the system clock in crystal mode If MOOCK is low during reset an external clock source at the EXTAL pin furnishes the system clock output in external clock mode Port 80 This pin can be used as a port Bparallel I O 2 11 INSTRUMENTATION AND EMULATION SIGNALS These signals are used for test or software debugging See Section 5 CPU32 for more information on these signals and backgro...

Page 45: ...ither a source or destination See Section 6 DMA Module for additional information on these signals 2 12 1 DMA Request DREQ2 DREQ1 This active low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory The assertion of DREQx starts the DMA process The assertion level in external burst mode is level sensitive in external cycle steal mode it is fall...

Page 46: ...DA TxDB These Signals are the transmitter serial data output for each channel The output is held high mark condition when the transmitter is disabled idle or operating in the local loopback mode Data is shifted out on this signal at the falling edge of the clock source with the least Significant bit transmitted first 2 13 5 Clear to Send CTSA CTSB These active low signals can be programmed as the ...

Page 47: ...er contains a character FFULLA When used for this function this signal reflects the complement of the status of bit 1 of the interrupt status register This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full OP4 When used for this function this output is controlled by bit 4 in the output port data registers 2 14 TIMER SIGNALS The fo...

Page 48: ...ard 2 15 4 Test Data Out TOO This output is used for serial test instructions and test data for on board test logic defined by the IEEE 1149 1 standard 2 16 SYNTHESIZER POWER VCCSYN This pin supplies a quiet power source to the VCO to provide greater frequency stability It is also used to control the synthesizer mode after reset See Section 4 System Integration Module for more information 2 17 SYS...

Page 49: ...d Modify Write Cycle l lMC Out Low Yes Address Strobe AS Out Low Yes Data Strobe OS Out Low Yes Size SIZ1 SIZO Out Yes Read Write R W Out High Low Yes Interrupt Request Level IR07 IROS TA05 In I O Low Port B7 B6 B5 B3 IR03 Reset RESET I O Low No Halt HALT I O Low No Bus Error BERR In Low System Clock CLKOUT Out No Crystal Oscillator EXTAL XTAL In Out External Filter Capacitor XFC In Clock Mode Sel...

Page 50: ...Out Low No Receiver Ready RxRDYA Out Out Out Low Low No FIFO Full OP4 DMA Request DRrn2 15REQf In Low DMA Acknowledge DACK2 DACK1 Out Low No DMADone OONE2 OONE1 I O Low No Timer Gate TGATE2 TGATE1 In Low Timer Input TIN2 TIN1 In Timer Output TOUT2 TOUT1 Out Yes Test Clock TCK In Test Mode Select TMS In High Test Data In TOI In High Test Data Out TOO Out High Synchronizer Power VCCSYN System Power ...

Page 51: ...2 16 MC68340 USER S MANUAL MOTOROLA ...

Page 52: ...ng a bus transfer is defined as the port width The MC68340 contains an address bus that specifies the address for the transfer and a data bus that transfers the data Control signals indicate the beginning and type of the cycle as well as the address space and size of the transfer The selected device then controls the length of the cycle with the signal s used to terminate the cycle Strobe signals ...

Page 53: ...tion indicates that a signal is inactive or false 3 1 1 Bus Control Signals The MC68340 initiates a bus cycle by driving the A31 AO SIZx FCx and RIW outputs At the beginning of a bus cycle SIZ1 and SIZO are driven with FC3 FCO SIZ1 and SIZO indicate the number of bytes remaining to be transferred during an operand cycle consisting of one or more bus cycles Table 3 1 lists the encoding of the SIZx ...

Page 54: ...unction codes are automatically generated by the CPU32 to select address spaces for data and program at both user and supervisor privilege levels a CPU address space for processor functions and an alternate master address space User programs access only their own program and data areas to increase protection of system integrity and can be restricted from accessing other information The S bit in th...

Page 55: ...ice that the data to be written is valid The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle 3 1 7 Bus Cycle Termination Signals The following signals can terminate a bus cycle 3 1 7 1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS DSACK1 AND DSACKO During bus cycles external devices assert DSACK1 and or DSACKO as part of the bus protocol During a read c...

Page 56: ...her externally or internally by the SIM40 see Section 4 System Integration Module for additional information AVEC is ignored during all other bus cycles 3 2 DATA TRANSFER MECHANISM The MC68340 supports byte word and long word operands allowing access to 8 and 16 bit data ports through the use of asynchronous cycles controlled by DSACK1 and DSACKO The MC68340 also supports byte word and long word o...

Page 57: ... the figures and descriptions that follow Figure 3 2 shows the required organization of data ports on the MC68340 bus for both 8 and 16 bit devices The four bytes shown in Figure 3 2 are connected through the internal data bus and data multiplexer to the external data bus The data multiplexer establishes the necessary connections for different combinations of address and data sizes The multiplexer...

Page 58: ... byte operand is properly aligned at any address a word or long word operand is misaligned at an odd address At most each bus cycle can transfer a word of data aligned on a word boundary If the MC68340 transfers a long WOrd operand over a 16 bit port the most significant operand word is transferred on the first bus cycle and the least significant operand word is transferred on a following bus cycl...

Page 59: ... 3 2 BYTE OPERAND TO 16 BIT PORT EVEN AO 0 The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single byte operand BYTE OPERAND Pp 7 0 DATA BUS 015 OS 07 DO Sill SilO AD DSACK1 DSACKO CYCLE 1 I oPO I OPO I 0 0 0 X For a read operation the slave responds by placing data on bits 15 8 of the data bus and asserting DSACK1 to indicate a i6 bit port The MC68340 th...

Page 60: ...s with the desired address and the SIZx pins to indicate a word operand WORD OPERAND I OPO I OPl 15 t 87 0 DATA BUS 015 08 07 00 SlZl SIZO AD DSACKl DSACKO CYCLE 1 I oPO I IOP1 I CYCLE2 _ OPl _ OP1 _ o o 1 o 0 1 0 For a read operation the slave responds by placing the most significant byte of the operand on bits 15 8 of the data bus and asserting DSACKO to indicate an 8 bit port The MC68340 reads ...

Page 61: ...ation shown in Figure 3 3 the slave responds by placing the most Significant byte of the operand on bits 15 8 of the data bus and asserting DSACKO to indicate an 8 bit port The MC68340 reads the most significant byte of the operand byte 0 from bits 15 8 and ignores bits 7 0 The MC68340 then decrements the transfer size counter increments the address initiates a new cycle and reads byte 1 of the op...

Page 62: ...FCO X X OC OC K 1 1 I 1 1 1 81ZO I 1 V f 4BYTES 3BVTES 2BYTES 1BYTE V I 1 8111 r 1 1 r Ir r 1 015 08 OPO J OP1 I OP3 J 07 00 BYTE BYTE BYTE BYTE READ READ READ READ LONG WORD OPERANO READ FROM 8 B1T BUS Figure 3 3 Long Word Operand Read Timing from 8 81t Port MOTOROLA MC68340 USER S MANUAL 3 11 ...

Page 63: ...I I WRITE WRITE WRITE WRITE LONG WORD OPERAND WRITE TO 8 BIT BUS Figure 3 4 Long Word Operand Write Timing to 8 Bit Port 3 2 3 7 LONG WORD OPERAND TO 16 BIT PORT ALIGNED Figure 3 5 shows both long word and word read and write timing to a 1S bit port LONG WORD OPERAND I OPO I OPI I OP2 I OP3 I I 31 23 15 7 0 DATA BUS D15 os D7 DO Sill SIZO AD DsAcK1 DSACKO CYCLE 1 I OPO OPI I 0 0 0 0 X CYCLE 2 OP2 ...

Page 64: ...acing the two most significant bytes of the operand on bits 15 0 of the data bus and asserting DSACK1 to indicate a 16 bit port The MC68340 reads the two most significant bytes of the operand bytes 0 and 1 from bits 15 0 The MC68340 then decrements the transfer size counter by 2 increments the address by 2 initiates a new cycle and reads bytes 2 and 3 of the operand from bits 15 0 of the data bus ...

Page 65: ...a minimum of three clock cycles when the cycle is terminated with DSACKx the MC68340 inserts wait cycles in clock period increments until DSACKx is recognized BERR and or HALT can be asserted after DSACKx is asserted BERR and or HALT must be asserted within the time specified after DSACKx is asserted in any asynchronous system If this maximum delay time is violated the MC68340 may exhibit erratic ...

Page 66: ...he chip select circuit fast termination enable FTE can provide a two clock external bus transfer Since the chip select circuits are driven from the system clock the bus cycle termination is inherently synchronized with the system clock Refer to Section 4 System Integration Module for more information on chip selects When fast termination is selected the DD bits of the corresponding address mask re...

Page 67: ...iptions and timing diagrams of data transfer cycles are independent of the clock frequency Bus operations are described in terms of external bus states 3 3 1 Read Cycle During a read cycle the MC68340 receives data from a memory or peripheral device If the instruction specifies a long word or word operation the MC68340 attempts to read two bytes at once For a byte operation the MC68340 reads one b...

Page 68: ... the start of state 3 S3 the MC68340 inserts wait states instead of proceeding to states 4 and 5 To ensure that wait states are inserted both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2 If wait states are added the MC68340 continues to sample DSACKx on the falling edges of the clock until one is recognized State 4 At the falling...

Page 69: ...340 asserts AS indicating a valid address on the address bus State 2 0uring S2 the MC68340 places the data to be written onto 015 00 and samples OSACKx at the end of S2 State 3 The MC68340 asserts OS during S3 indicating that data is stable on the data bus As long as at least one of the OSACKx signals is recognized by the end of S2 meeting the asynchronous input setup time requirement the cycle te...

Page 70: ...ead Modify Write Cycle The read modify write cycle performs a read conditionally modifies the data in the arithmetic logic unit and may write the data out to memory In the MC68340 this operation is indivisible providing semaphore capabilities for multiprocessor systems During the entire read modify write sequence the MC68340 asserts RMC to indicate that an indivisible operation is occurring The MC...

Page 71: ...one read cycle is required to read in the operand s SO 55 are repeated for each read cycle When finished reading the MC68340 holds the address RIW and FC3 FCO valid in preparation for the write portion of the cycle The external device keeps its data and OSACKx signals asserted until it detects the negation of AS or OS whichever it detects first The device must remove the data and negate OSACKx wit...

Page 72: ... remove its data and negate OSACKx within approximately one clock period after sensing the negation of AS or OS 3 4 CPU SPACE CYCLES FC3 FCO select user and supervisor program and data areas The area selected by FC3 FCO 7 is classified as the CPU space The breakpoint acknowledge LPSTOP broadcast module base address register access and interrupt acknowledge cycles described in the following paragra...

Page 73: ... in the internal instruction pipeline and then begins execution of that instruction When the CPU32 acknowledges a BKPT pin assertion hardware breakpoint with background mode disabled the CPU32 performs a word read from CPU space type O at an address corresponding to all ones on A4 A2 BKPT 7 and the T bit A1 is set If this bus cycle is terminated by BERR the MC68340 performs hardware breakpoint exc...

Page 74: ... and is shown externally to indicate to external devices that the MC68340 is going into LPSTOP mode If an external device requires additional time to prepare for entry into LPSTOP mode entry can be delayed by asserting HALT The SIM40 provides internal DSACKx response to this cycle For more information on how the SIM40 responds to LPSTOP mode see Section 4 System Integration Module 15 14 13 12 11 1...

Page 75: ... GO TO A IF BKPT PIN ASSERlED AND DSACKx IS ASSERlED 1 NEGATEASANDDS 2 GO TO A IF BERR ASSERTED 1 NEGATEASANDDS 2 GO TO B A B I IF BREAKPOINT INSTRUCTION EXECUTED 1 PLACE LATCHED DATA IN INSTRUCTION PIPELINE 2 CONTINUE PROCESSING IF BKPT PIN ASSERlED 1 CONTINUE PROCESSING IF BREAKPOINT INSTRUCTION EXECUTED 1 INITIATE UEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERlED 1 INITIATE HARDWARE BREAKPOINT ...

Page 76: ...BERIT P I A15 AS AO I Jo lr FC3 fCO ______ 0 CPU SPACE C SIZO x ____ tl SIZ1 _ _ _ _ J L _ j _ t __ J 07 00 q c r C 015 08 q CY BERR j H T J Jo __ 1 _ 1 4 _____ J 4 FETCHED I INSTRUCTIONI BREAKPOINT t If READ E A E 1 iXECUTIO I OCCURS INSTRUCTION WORD FETCH Figure 3 12 Breakpoint Acknowledge Cycle Timing Opcode Returned MOTOROLA MC68340 USER S MANUAL 3 25 ...

Page 77: ...ERfT BO_ _ _ _ _ I Al5 A5 AO r Ir 3 26 FCHCO J _ I CPU SPACE SilO J x lr l Ar J r _ SIZl J ____ J ____ L _ r _____7 07 00 ql c J r 015 08 q CJ BERR J HALT J L JG r __ 17 BREAKPOINT _ Cf READ i CE ACKNOWlEDGE 1 r I I BREAKPOINT OCCURS BUS ERROR ASSERTED Figure 3 13 Breakpoint Acknowledge Cycle Timing Exception Signaled MC68340 USER S MANUAL MOTOROLA ...

Page 78: ...rupt must be removed for one clock cycle before a second level 7 can be recognized The third case occurs if upon returning from servicing a level 7 interrupt the request level stays at 7 and the processor mask level changes from 7 to a lower level a second level 7 is recognized The CPU32 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any other...

Page 79: ... the least significant byte of its data port for an 8 bit port the vector number must be on 015 08 for a 16 bit port the vector must be on 07 00 during the interrupt acknowledge cycle The cycle is then terminated normally with OSACKX Figure 3 14 is a flowchart of the interrupt acknowledge cycle Figure 3 15 shows the timing for an interrupt acknowledge cycle terminated with OSACKX INTERRUPTING DEVI...

Page 80: ...cycles Figure 3 15 Interrupt Acknowledge Cycle Timing 3 4 4 2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE When the interrupting device cannot supply a vector number it requests an automatically generated vector autovector Instead of placing a vector number on the data bus and asserting DSACKx the device asserts AVEC to terminate the cycle If the DSACKx signals are asserted during an interrupt acknowled...

Page 81: ... distinct autovectors can be used corresponding to the seven levels of interrupt available with signals IRQ7 iR01 Figure 3 16 shows the timing for an autovector operation 3 4 4 3 SPURIOUS INTERRUPT CYCLE Requested interrupts whether internal or external are arbitrated internally When no internal module including the SIM40 which responds for external requests responds during an interrupt acknowledg...

Page 82: ...D INTERRUPT LEVEL lX A3 Al D V NJ FC3 fCO D D PUSPACE X D V 1BYTE SIZO D Sill 1 V V r A r II J II D1s DO 1 AVEC 7 1 ___ CYCLE INTERNAL READ ARBITRATION K CYCLE Internal Arbitration may take between 0 2 clocks Figure 3 16 Autovector Operation Timing MOTOROLA UC68340 USER S MANUAL 3 31 ...

Page 83: ...uitry to provide these signals Alternatively the internal bus monitor could be used The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACKx assertion as follows case numbers refer to Table 3 4 Normal Termination DSACKx is asserted BERR and HALT remain negated case 1 Halt Termination HALT is asserted at the same time as or before DSACKx and BERR remains ne...

Page 84: ... the next clock cycle case 6 The memory controller can then correct the RAM prior to or during the automatic retry Table 3 4 DSACKi BERR and HALT Assertion Results Asserted on Rising Edge of State case Control Num Signal N N 2 Result 1 A S Normal cycle terminate and continue BERR NA NA HAC NA X 2 A S Normal cycle terminate and halt continue BERR NA NA when HAC negated HAC AIS S 3 NAJA X Terminate ...

Page 85: ...g cases DSACKx and HALT are negated and BEAR is asserted HALT and BERR are negated and DSACKx is asserted BERR is then asserted within one clock cycle HALT remains negated BERR and HALT are asserted simultaneously indicating a retry When the MC68340 recognizes a bus error condition it terminates the current bus cycle in the normal way Figure 3 17 shows the timing of a bus error for the case in whi...

Page 86: ...CLKOUT A31 AO FC3 FCO 015 00 1 1 4J I 1 Figure 3 17 Bus Error without DSACKX MOTOROLA MC68340 USER S MANUAL 3 35 ...

Page 87: ... signal described previously can also occur see Figure 3 20 The MC68340 terminates the bus cycle places the control signals in their inactive state and does not begin another bus cycle until the BERR and HALT signals are negated by external logic After a synchronization delay the MC68340 retries the previous cycle using the same access information address function code size etc BERR should be nega...

Page 88: ...ng with BERR and HALT provides a relinquish and retry operation The MC68340 does not relinquish the bus during a read modify write operation Any device that requires the MC68340 to give up the bus and retry a bus cycle during a read modify write cycle must assert only BERR and BR HALT must not be included The bus error handler software should examine the read modify write bit in the special status...

Page 89: ...nal MC68340 operations one bus cycle at a time Since the occurrence of a bus error while HALT is asserted causes a retry operation the user must anticipate retry cycles while debugging in the single cycle mode The single step operation and the software trace capability allow the system debugger to trace single bus cycles single instructions or changes in program flow When the MC68340 completes a b...

Page 90: ...ITTED WHILE THE PROCESSOR IS HALTED Figure 3 21 HALT Timing 3 5 4 Double Bus Fault so r K K r A double bus fault results when a bus error or an address error occurs during the exception processing sequence for any of the following A previous bus error A previous address error A reset For example the MC68340 attempts to stack several words containing information about the state of the machine while...

Page 91: ...having several devices that can become bus master require external circuitry to assign priorities to the devices so that when two or more external devices attempt to become bus master at the same time the one having the highest priority becomes bus master first The sequence of the protocol is as follows 1 An external device asserts BA 2 The MC68340 asserts BG to indicate that the bus is available ...

Page 92: ...s external arbitration circuitry to select the next bus master before the current bus master has finished using the bus The following paragraphs provide additional information about the three steps in the arbitration process Bus arbitration requests are recognized during normal processing HALT assertion and a CPU32 halt caused by a double bus fault PROCESSOR REQUESTING DEVICE REQUEST THE BUS GRANT...

Page 93: ... I Figure 3 23 Bus Arbitration Timing Diagram Idle Bus Case so Sl S2 S3 S4 S5 CLKOUT A31 MJ J 015 00 J AS r os I FWi OSACKO OSACKI iiR BG I BGACK Figure 3 24 Bus Arbitration Timing Diagram Active Bus Case 3 42 MC68340 USER S MANUAL MOTOROLA ...

Page 94: ...ter BA is asserted depends on internal synchronization see Section 11 Electrical Characteristics During an external operand transfer the MC68340 does not assert BG until after the last cycle of the transfer determined by SIZx and DSACKx During an external operand transfer the MC68340 does not assert BG as long as RMC is asserted If the show cycle bits SHEN1 5HENO 01 the MC68340 does not assert BGt...

Page 95: ... R and A keep the arbiter in state 0 as long as they are both negated The MC68340 does not allow arbitration of the external bus during the RMC sequence For the duration of this sequence the MC68340 ignores the BR input If mastership of the bus is required during an RMC operation BERR must be used to abort the RMC sequence I 3 6 5 Show Cycles The MC68340 can perform data transfers with its interna...

Page 96: ... RA R BUS REQUEST A BUS GRANTACKNOWLEDGE B BUS CVa E IN PROGRESS G BUSGRANT T THREE STATE SIGNAL TO BUS CONTROL V BUS AVAlABLE TO BUS CONTROL Figure 3 25 Bus Arbitration State Diagram MC68340 USER S MANUAL 3 45 ...

Page 97: ...l data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus State o The A31 AO FCx RIW and SIZx pins change to begin the next cycle Data from the preceding cycle is valid through state O so 841 842 S43 so Sl S2 CLKOUT A31 AO X X FC2 fCO S1Z1 1ZO Alii x X AS CS os I D15 DO BKPT L I SHOW CYClE 10 1 START OF EXTERNALCYCLE j Figure 3 26 ...

Page 98: ...rnal RESET is released When the reset control logic detects that external RESET is no longer being driven it drives both internal and external reset low for an additional 512 cycles to guarantee this length of reset to the entire system Figure 3 27 shows the RESET timing ra RESET II I 590CLOCK n4 512CLOCK PUUED RNAL lI DRIVENBY MC6834O J t lgure 3 27 Timing for External Devices Driving RESET If re...

Page 99: ...r Up Reset Timing Diagram When a RESET instruction is executed the MC68340 drives the RESET signal for 512 clock cycles The SIM40 registers and the module control registers in each internal peripheral module DMA timers and serial modules are not affected All other peripheral module registers are reset the same as for a hardware reset The external devices connected to the RESET signal are reset at ...

Page 100: ...i ii u u iiu all iUI IIiil C1i j juw v r rllCUlY oj me omer Tealures In me IM S differ in their use and details The system configuration and protection function controls system configuration and provides various monitors and timers including the internal bus monitor double bus fault monitor spurious interrupt monitor software watchdog timer and the periodic interrupt timer The clock synthesizer ge...

Page 101: ...on and protection clock synthesizer chip select functions and the external bus interface NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation...

Page 102: ...e basic concepts of safeguarded design present in all M68000 members In addition many functions that normally must be provided by external circuits are incorporated in this device The following features are provided in the system configuration and protection function SIM40 Module Configuration The SIM40 allows the user to configure the system to the particular requirements The functions include co...

Page 103: ... is loading information from a bus error stack frame during an RTE instruction This function can be disabled See Section 3 Bus Operation for more information Spurious Interrupt Monitor If no interrupt arbitration occurs during an interrupt acknowledge lACK cycle the bus error signal is asserted internally This function cannot be disabled Software Watchdog The software watchdog asserts reset or a l...

Page 104: ... accesses can be shown on the external bus This function is called show cycles The SHEN1 SHENO bits in the MCR control show cycles Bus arbitration can be either enabled or disabled during show cycles Arbitration for servicing interrupts is controlled by the value programmed into the interrupt arbitration IARB field of the MCR Each module that generates interrupts including the SIM40 has an IARB fi...

Page 105: ...n this case the internal to external bus monitor option must be disabled The bus cycle termination response time is measured in clock cycles and the maximum allowable response time is programmable The bus monitor response time period ranges from 8 to 64 system clocks seelable 4 8 These options are provided to allow for different response times of peripherals that might be used in the system 4 2 2 ...

Page 106: ...C INTERRUPT TIMER The periodic interrupt timer consists of an 8 bit modulus counter that is loaded with the value contained in the PITR see Figure 4 3 The modulus counter is clocked by a signal derived from the EXTAL input pin unless an external frequency source is used When an external frequency source is used MODCK low during reset the default state of the prescaler control bits SWP and PTP in t...

Page 107: ...of 01 00000001 binary to 31 128 ms with a PITR value of FF 11111111 binary Solving the equation with the prescaler enabled PTP 1 in the PITR gives the following values PITR count value periodic interrupt timer period 32768 512 periodic interrupt timer period PITRcount value 16 This gives a range from 62 5 ms with a PITR value of 01 to 15 94 s with a PITR value of FF For fast calculation of periodi...

Page 108: ... of clock operation are listed in Table 4 1 Table 4 1 Clock Operating Modes MOOCK VCCSYN Mode Description Reset Operating Value Value External crystal or oscillator used wkh the on chip PLL and VCO to Crystal Mode generate a system clock and CLKOUT of programmable rales 5V 5V External Clock The desired operating frequency is driven into EXTAL resulting in a Mode without PLL system clock and CLKOUT...

Page 109: ...lator CLKOur A separate power pin VCCSYN is used to allow the clock circuits to run with the rest of the device powered down and to provide increased noise immunity for the clock circuits The source for VCCSYN should be a quiet power supply with adequate external bypass capacitors placed as close as possible to the VCCSYN pin to ensure a stable operating frequ ncy Figure 4 4 shows typical values f...

Page 110: ...nal of the same frequency as the input signal with a tight skew between the external clock and the internal clock and CLKOUT signals To enable this mode MOOCK must be held low during reset and VCCSYN should be connected to a quiet 5 V source If an input signal loss for either of the clock modes utilizing the PLL occurs chip operation can continue in limp mode with the VCO running at approximately ...

Page 111: ...parator The frequency divider consists of 1 a 2 bit prescaler controlled by the W bit in the SYNCR and 2 a 6 bit modulo downcounter controlled by the Y bits in the SYNCR Several factors are important to the design of the system clock The resulting system clock frequency must be within the limits specified for the device The frequency of the system clock is given by the following equation FSYSTEM F...

Page 112: ...and STSIM bits in the SYNCR control clock activity during LPSTOP Refer to 4 2 6 Low Power Stop for additional information Table 4 3 Clock Control Sianals Control Bits Clock Outputs STSIM STEXT SIMCLK CLKOUT 0 0 EXTAL Off 0 1 EXTAL EXTAL 1 0 veo Off 1 1 veo veo NOTE SIMCLK runs the periodic interrupt RESET and IRQx pin synchronizers in LPSTOP mode 4 2 4 Chip Select Operation Typical microprocessor ...

Page 113: ...bits 15 8 the 16 bit ports can be accessed as odd bytes even bytes or even words The port size is specified by the PS bits in the address mask register Write Protect Capability The WP bit in each base address register can restrict write access to its range of addresses Fast Termination Option Programming the FTE bit in the base address register for the fast termination option causes the chip selec...

Page 114: ...an use an 8 bit boot ROM if an external 8 bit DSAGKx that responds in two or less wait states is generated The 8 bit DSAGKx must respond in two or less wait states so that the global chip select which responds with three wait states will not be used See Section 10 Applications for a detailed discussion 4 2 5 External Bus Interface Operation This section describes port A and port B functions Refer ...

Page 115: ...OCK IR07 IR06 IR05 IR03 and CS3 CSO MODCKIPORT eo IR07IPORT B7 IR06IPORT B6 INTERRUPT IRQ5IPORT B5 PORT IR03JPORlB3 LOGIC IR04IPORT B4 IR02lPORT B2 IR01IPORT B1 CS3 IR04IPORT B4 AVEC CS2 IR02IPORT B2 FULL IRQ MUX CSlIIR01IPORT B1 CS3 CSO AVEC CHIP CS2 SELECT CS1 MODULE CSO FIRQ f Figure 4 7 Full Interrupt Request Multiplexer Table 4 5 Port B Pin Assignment Register Pin Function Signal FIRQ O FIRQ ...

Page 116: ... it can be used to exit LPSTOP as long as the interrupt request level is higher than the CPU32 interrupt mask level To stop the periodic interrupt timer while in LPSTOP the PITA must be loaded with a zero value before LPSTOP is executed The bus monitor double bus fault monitor and spurious interrupt monitor are all inactive during LPSTOP The STP bit in the MCA of each on chip module DMA timers and...

Page 117: ...ndicates whether a register is restricted to supervisor access S or programmable to exist in either supervisor or user space S U For the registers discussed in the following pages the number in the upper right hand corner indicates the offset of the register from the address stored in the module base address register The numbers on the top line of the register represent the bit position in the reg...

Page 118: ...ON CONTROL SYPCR PERIODIC INTERRUPT CONTROL REGISTER PICR PERIODIC INTERRUPT TIMING REGISTER PITR RESERVED SOFTWARE SERVICE SWSR I SYSTEM PROTECTION CLOCK SYSTEM PROTECTION EBI EBI EBI EBI EBI EBI EBI EBI SYSTEM PROTECTION SYSTEM PROTECTION SYSTEM PROTECTION SYSTEM PROTECTION 1 ________ A_D_DR_E_S_S_M_A_S_K_1_C_S_0______ I1CHIP SELECT ADDRESS MASK 2 CSO CHIP SELECT BASE ADDRESS 1CSO BASE ADDRESS 2...

Page 119: ...d an access to the register block location in that address space becomes an external access The module block is not accessed The address space bits are as follows AS8 mask DMA Space address space FC3 FCO 1xxx AS7 mask CPU Space address space FC3 FCO 0111 AS6 mask Supervisor Program address space FC3 FCO 0110 ASS mask Supervisor Data address space FC3 FCO 0101 AS4 mask Reserved Motorola address spa...

Page 120: ...ad AO with the address of MBAR load DO with the value to be written into MBAR write the value contained in DO into MBAR 4 3 2 System Configuration and Protection Registers The following paragraphs provide descriptions of the system configuration and protection registers 4 3 2 1 MODULE CONFIGURATION REGISTER MCR The MCR which controls the 0 VIIYI U VUI III t IUICUIUI I rail Ie It7au VI YVI ILL Cr1 ...

Page 121: ...quest until arbitration is enabled again To prevent bus conflicts external peripherals must not attempt to initiate cycles during show cycles with arbitration disabled Table 4 6 SHENx Control Bits SHEN1 SHENO ACTION 0 0 Show cycles disabled external arbitration enabled 0 1 Show cycles enabled external arbitration disabled 1 X Show cycles enabled external arbitration enabled SUPV Supervisor User Da...

Page 122: ...l interrupts 4 3 2 3 RESET STATUS REGISTER RSR The RSR contains a bit for each reset source to the SIM40 A set bit indicates the last type of reset that occurred and only one bit can be set in the register The RSR is updated by the reset control logic when the SIM40 comes out of reset This register can be read at any time a write has no effect For more information see Section 3 Bus Operation RSR 0...

Page 123: ...0 during an lACK cycle in response to an interrupt generated by the software watchdog This register can be read or written at any time This register is set to the uninitialized vector OF at reset SWIV RESET o o 020 o o Supervisor Only 4 3 2 5 SYSTEM PROTECTION CONTROL REGISTER SYPCR The SYPCR controls the system monitors the prescaler for the software watchdog and the bus monitor timing This regis...

Page 124: ...t Frequency 8s 15 6 ms 1 0 1 220 EXTAL Input Frequency 32s 62 5 ms 1 1 0 222 EXTAL Input Frequency 128 s 250ms 1 1 1 224 EXTAL Input Frequency 512 s 1 s NOTE When the SWP and SWT bits are modified to select a software timeout other than the default the software service sequence 55 followed by AA written to the software service register must be performed before the new timeout period takes effect R...

Page 125: ... the periodic interrupt request level Table 4 9 lists which interrupt request level is asserted during an lACK cycle when a periodic interrupt is generated The periodic timer continues to run when the interrupt is disabled 4 26 Table 4 9 PIRQL Encoding PIROL2 PIROL1 PIROLO Interrupt Request Level 0 0 0 Periodic Interrupt Disabled 0 0 1 Interrupt Request Levell 0 1 0 Interrupt Request Level 2 0 1 1...

Page 126: ... not affect these bits PITR 024 RESET o o o o Bits 15 1 o Reserved o o MODel MODel 0 SWP Software Watchdog Prescale o o o o o o o Supervisor Only This bit controls the software watchdog clock source as shown in 4 3 2 5 System Protection Control Register SYPCR 1 Software watchdog clock prescaled by a value of 512 0 Software watchdog clock not prescaled The SWP reset value is the inverse of the MOOC...

Page 127: ... W I X VS V4 V3 V2 VI RESET o o o o o u u o o o U Unaffected by reset Supervisor Only W Frequency Control Bit This bit controls the prescaler tap in the synthesizer feedback loop Setting the bit increases the VCO speed by a factor of 4 requiring a time delay for the VCO to relock see equation for determining system frequency X Frequency Control Bit This bit controls a divide by two prescaler which...

Page 128: ...top Mode System Integration Clock 1 When LPSTOP is executed the SIM40 clock is driven from the VCO 0 When LPSTOP is executed the SIM40 clock is driven from an external crystal or oscillator and the VCO is turned off to conserve power STEXT Stop Mode External Clock 1 When the LPSTOP instruction is executed the external clock pin CLKOUT is driven from the SIM40 clock as determined by the STSIM bit o...

Page 129: ...re are nine function code address spaces see Section 3 Bus Operation specified as either user or supervisor program or data CPU and DMA These bits should be used to allow access to one type of address space If access to more than one type of address space is desired the FCMx bits should be used in addition to the BFCx bits To prevent access to CPU space set the NCS bit WP Write Protect This bit ca...

Page 130: ... 3 4 2 ADDRESS MASK REGISTERS There are four 32 bit address mask registers in the chip select function one for each chip select signal Address Mask 1 040 048 050 058 RESET U U U U U U U U U U U U U U U u Supervisor Only Address Mask 2 042 04A 052 05A 14 13 12 11 10 RESET U U U U U U U U U U U U U U U U U Unaffected by reset Supervisor Only AM31 AM8 Address Mask Bits 31 8 The address mask field the...

Page 131: ...d earlier than indicated by the DDx bits the cycle will terminate sooner than programmed See 4 2 5 2 PORT B for a discussion on using the internal DSACKx generation without using the CSx signal Table 4 10 DDx Encoding 001 000 Response 0 0 Zero Wait State 0 1 One Wait State 1 0 Two Wait States 1 1 Three Wait States PS1 PSo Port Size Bits 1 and 0 This field determines whether a given chip select res...

Page 132: ...rs that control the I O pins used with the EBI Refer to the Section 3 Bus Operation for more information about the EBI For a list of pin numbers used with port A and port B see the pinout diagram in Section 12 Ordering Information and Mechanical Data Section 2 Signal Descriptions shows a block diagram of the port control circuits 4 3 5 1 PORT A PIN ASSIGNMENT REGISTER 1 PPARA1 PPARA1 selects betwe...

Page 133: ...TER DORA DORA controls the direction of the pin drivers when the pins are configured as 1 0 Any set bit configures the corresponding pin as an output Any cleared bit configures the corresponding pin as an input This register affects only pins configured as discrete 1 0 This register can be read or written at any time DORA 013 7 6 5 4 3 2 1 I 007 I DDS I DDS I DD4 I 003 I DD2 I 001 I ODO I RESET o ...

Page 134: ...as an output any cleared bit configures the corresponding pin as an input This register affects only pins configured as discrete 1 0 This register can be read or written at any time DDRB 01D 7 6 5 4 3 2 1 I007 IDD6 IDDS IDD4 IDD3 I002 I001 IDDO I RESET 0 0 0 0 0 0 0 0 SupervisorlUser 4 l 7 COAT A nATA CC r I TC C CnCTD OnOTDof Ta _ _ _ __1 _ _ t _ _ be accessed at two different addresses This regi...

Page 135: ...he desired base address for the internal modules 4 4 2 SIM40 Module Configuration The order of the following SIM40 register initializations is not important however time can be saved by initializing the SYNCR first to quickly increase to the desired processor operating frequency The module base address register must be initialized prior to any of following steps Clock Synthesizer Control Register ...

Page 136: ...r program a zero value to turn off the periodic timer PITRx bits Periodic Interrupt Control Register PICR If using the periodic timer program the desired interrupt level for the periodic interrupt timer PIRQLx bits If using the periodic timer program the vector number for a periodic timer interrupt vmp elect tsase AOOress ana AOOress Mask Registers Initialize and set the V bits in the necessary ch...

Page 137: ...stem stack pointer and initial PC respectively are located at offset 0 after reset equates SSP_INIT EQU 10000 Stack pointer initial value top of RAM MBAR EQU 0003FFOO Address of Module Base Address Reg MODBASE EQU FFFFFOOO Default Module Base address value SIM40 register offsets from MBAR base address MCR EQU 00 SYNCR EQU 04 SYPCR EQU 21 CSAMO EQU 40 CSBARO EQU 44 CSAM1 EQU 48 CSBAR1 EQU 4c CSAM2 ...

Page 138: ...om 8 3 to 16 7 MHZ MOVE W 7FOO SYNCR MOOBASE X bit doubles the default speed Module configuration register When FREEZE is asserted software watchdog and periodic interrupt timer are disabled bus monitor is enabled Port B 4 IROs 4 chiD selects Show Cycles enabled external arbitration enabled Supervisor user SIM registers unrestricted Interrupt Arbitration at priority F MOVE W 420F MCR MOOBASE Now s...

Page 139: ...RO DC L 000S0009 CS1 RAM OOOOOOOO OOOOffff fast termination CSAM1 DC L OOOOFFFO CSBAR1 DC L 00000005 CS2 external device 00FFE8xx external termination CSAM2 DC L 000000F3 CSBAR2 DC L OOFFE801 CS3 secondary memory 00000000 0003ffff 3 wait states 1S bit term CSAM3 DC L 0003FFFD CSBAR3 DC L 00000001 END 4 40 MC68340 USER S MANUAL MOTOROLA ...

Page 140: ...shutting down the CPU32 and other 1MB modules greatly reducing power consumption Ease of programming is an important consideration when using an integrated processor 7 0 v 2 ill ilu liull lurrllCu reflects a preaomlnate register memory interaction philosophy All data resources are available to all operations that require them The programming model includes eight multifunction data registers and se...

Page 141: ...f the CPU32 is shown in Figure 5 1 The major blocks depicted operate in a highly independent fashion that maximizes concurrences of operation while managing the essential synchronization of instruction execution and bus operation The bus controller loads instructions from the data bus into the decode unit The sequencer and control unit provide overall chip control managing the internal buses regis...

Page 142: ...res is the OBcc looping primitive instruction To increase the performance of the CPU32 a loop mode has been added to the processor The loop mode is used by any l iillgitl woro inslruCllon mat aoes not cnange tne program flow LOOp mode is implemented in conjunction with the OBcc instruction Figure 5 2 shows the required form of an instruction loop for the processor to enter loop mode ONE WORD INSTR...

Page 143: ...space Only the initial reset vector is fixed in the processor s memory map once initialization is complete there are no fixed assignments Since the VBR provides the base address of the vector table the vector table can be located anywhere in memory it can even be dynamically relocated for each task that is executed by an operating system Refer to 5 5 Exception Processing for additional details 31 ...

Page 144: ...e M68000PM AD M68000 Family Programmer s Reference Manual 5 1 7 Instruction Set The instruction set of the CPU32 is very similar to that of the MC68020 see Table 5 1 Two new instructions have been added to facilitate embedded control applications lPSTOP and table lookup and interpolate TBl The following M68020 instructions are not implemented on the CPU32 BFxxx CAllM RTM CAS CAS2 cpxxx PACK UNPK B...

Page 145: ...st Upper and RESET Reset External Devices Lower Bounds ROL ROR Rotate Left and Right ClR Clear Operand ROXL ROXR Rotate with Extend Left and Right CMP Compare RTD Return and Deallocate CMPA Compare Address RTE Return from Exception CMPI Compare Immediate RTR Return and Restore CMPM Compare Memory RTS Return from Subroutine CMP2 Compare Register against Upper SBCD Subtract Decimal with Extend and L...

Page 146: ...terrupts trap instructions tracing and other exception conditions The exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruction Externally exception processing can be forced by an interrupt a bus error or a reset The halted processing state is an indication of catastrophic hardware failure For example if during the ...

Page 147: ...r and Supervisor State Address Spaces Separate Program and Data Address Spaces Many Data Types Flexible Addressing Modes Full Interrupt Processing Expansion Capability 5 2 1 Programming Model The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels User programs can only use the registers of the user model The supervisor programmin...

Page 148: ...ael 31 1615 0 I I A7 SSP 87 0 I CCR I SR 31 0 I VBR 1 ___________________ E 3 2 0 1_ SFC DATAREGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAMCOUNTER CONDITIONCODE REGISTER SUPERVISORSTACK POINTER STATUS REGISTER VECTOR BASE REGISTER ALTERNATE FlKTlON CODE REGISTERS Figure 5 4 Supervisor Programming Model Supplement MOTOROLA MC68340 USER S MANUAL 5 9 ...

Page 149: ...tion codes reflect the results of a previous operation The codes are contained in the low byte CCR of the SA The interrupt priority mask determines the level of priority an interrupt must have to be acknowledged The control bits determine trace mode and privilege level At user privilege level only the CCR is available At supervisor privilege level software can access the full SA The VBR contains t...

Page 150: ... 1 M68000 Family Compatibility It is the philosophy of the M68000 Family that all user mode programs can execute unchanged on a more advanced processor and that supervisor mode programs and exception handlers should require only minimal alteration I ne Gf U32 can be thought of as an intermediate member of the M68000 family Object code from an MC68000 or MC68010 may be executed on the CPU32 and man...

Page 151: ...er supplied code to emulate unimplemented capabilities or to define special purpose functions However Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements See 5 5 2 8 Illegal or Unimplemented Instructions for more details 5 3 2 Instruction Format and Notation All instructions consist of at least one word Some instructions can hav...

Page 152: ...al contains detailed register information Except where noted the following notation is used in this section Data Destination Source Vector An AX Ay On Rc Rn Dh DI Dr Dq DX Dy Dym Dyn Xn An cc d ea data label list MOTOROLA Immediate data from an instruction Destination contents Source contents Location of exception vector Any address register A7 AO Address registers used in computation Any data reg...

Page 153: ...nt Arithmetic subtraction or predecrement Arithmetic division or conjunction symbol x Arithmetic multiplication Equal to Not equal to Greater than Greater than or equal to Less than S Less than or equal to A Logical AND V Logical OR e Logical exclusive OR Invert operand is logically complemented BCD Binary coded decimal indicated by subscript Example Source1 0 is a BCD source operand LSW Least sig...

Page 154: ...ogic Shift and rotate Bit manipulation Binary coded decimal arithmetic Program control System control The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development All CPU32 instructions are summarized in Table 5 2 MOTOROLA MC68340 USER S MANUAL 5 15 ...

Page 155: ...n true then PC d PC Bce label BCHG number of Destination Z BCHG Dn ea number of Destination bit number of BCHG data ea Destination BClR number of Destination Z BClR Dn ea o bit number of Destination BClR data ea BGND If background mode enabled then BGND enter background mode else FormaWector offset SSP PC SSP SR SSP Vector PC BKPT Run breakpoint acknowledge cycle BKPT data TRAP as illegal instruct...

Page 156: ... If supervisor state EORI data SR toSR the Source SR SR else TRAP EXG Rx Ry EXG DX Dy EXG Ax Ay EXG DX Ay EXG Ay Dx EXT Destination Sign Extended Destination EXT WDn extend byte to word EXTB EXT L On extend word to long word EXTB L On extend byte to long word LLEGAL SSP 2 SSP Vector Offset SSP ILLEGAL SSP 4 SSP PC SSP SSp 2 SSP SR SSP Illegal Instruction Vector Address PC JMP Destination Address P...

Page 157: ...DFC or Source MOVES ea Rn SFC Rn else TRAP MULS Source x Destination Destination MULS W ea Dn 16 x 16 32 MULS L ea DI 32 x32 32 MULS L ea Dh DI 32 x32 64 MULU Source x Destination Destination MULU W ea Dn 16 x 16 32 MULU L ea DI 32x32 32 MULU L ea Dh DI 32x32 64 NBCD 0 Destination1 0 X Destination NBCD ea NEG 0 Destination Destination NEG ea NEGX 0 Destination X Destination NEGX ea NOP None NOP NO...

Page 158: ...e X Destination Register 31 16 Register 15 0 esti t n T st Condition Codes ENTRY n ENTRY n 1 ENTRY n Dx 7 0 1256 Ox ENTRY n x 256 ENTRY n 1 ENTRY n Ox 7 0 Ox ENmY n ENTRY n 1 ENTRY n Dx 7 0 1256 Ox ENmY n 256 ENTRY n 1 ENmY n Ox 7 0 Ox SSP 2 SSP FormatlOffset SSP SSP 4 SSP PC SSP SSP 2 SSP SR SSP Vector Address PC If cc then TRAP If V then TRAP TST Destination Tested Condition Codes UNLK An SP SP ...

Page 159: ...m V Am A Om V Sm A Am Z ZARmA ARO AND ANDI EOR EORI 0 0 MOVEO MOVE OR ORI CLR EXT NOT TAS 18T CHK U U U CHK2 CMP2 U U Z R LB V R UB C LB UB A IR LB V R UB V UB LB A R UB A R LB SUB SUBI SUBO V SmA DmA AmVSmA DmARm C Sm A Om VRm A Om V Sm A Rm SUBX V SmA DmA AmV SmA OmARm C Sm A Om V Rm A Om V Sm A Rm Z Z A Rm A A RO CMP CMPI CMPM V SmADmA AmV SmA OmARm C Sm A Om V Rm A Om V Sm A Rm DIVS DIVU 0 V D...

Page 160: ...ly valid address manipulations are executed In addition to the general MOVE instructions there are several special data movement instructions move multiple registers MOVEM move peripheral data MOVEP move quick MOVEa exchange registers EXG load effective address LEA push effective address PEA link stack LINK and unlink stack UNLK Table 5 4 is a summary of the data movement operations Table 5 4 Data...

Page 161: ...operands Signed and unsigned MUL and DIV instructions include Word multiply to produce a long word product Long word multiply to produce a long WOrd or quad word product Division of a long Ward dividend by a word divisor word quotient and word remainder Division of a long ward or quad word dividend by a long word divisor long word quotient and long word remainder A set of extended instructions pro...

Page 162: ...32 16 16 16 DestinationlSource Destination signed or ea Dr Dq 64 32 32 32 unsigned ea Dq 32132 32 DIVSLlDIVUL ea Dr Dq 32 32 32 32 EXT Dn 8 16 Sign Extended Destination Destination On 16 32 EXTB Dn 8 32 Sign Extended Destination Destination MULSIMULU ea Dn 16x16 32 Source x Destination Destination signed or ea DI 32x32 32 unsigned ea Dh DI 32x32 64 NEG ea 8 16 32 0 Destination Destination NEGX ea ...

Page 163: ... ea 8 16 32 Immediate Data V Destination Destination TST ea 8 16 32 Source 0 to set condition codes 5 3 3 5 SHIFT AND ROTATE INSTRUCTIONS The arithmetic shift instructions ASR and ASL and logical shift instructions LSR and LSL provide shift operations in both directions The ROR ROL ROXR and ROXL instructions perform rotate circular shift operations with and without the extend bit All shift and rot...

Page 164: ...RT T hit tA t Inri At R FT hit test and clear BClR and bit test and change BCHG All bit manipulation operations can be performed on either registers or memory The bit number is specified as immediate data or in a data register Register operands are 32 bits long and memory operands are 8 bits long Table 5 8 is a summary of bit manipulation instructions Table 5 8 Bit Manipulation Operations Operand ...

Page 165: ...routine call and return instructions and conditional and unconditional branch instructions perform program control operations Table 5 10 summarizes these instructions Table 5 10 Program Control Operations Operand Instruction Syntax Operand Size Operation Conditional Bee label 8 16 32 If condition true then PC d PC OBee On label 16 If condition false then On 1 PC il On 1 then PC d PC See ea 8 II co...

Page 166: ...GT Greater than T True HI High VC Overflow clear LE Less or equal VS Overflow set Not applicable to the Bcc instruction 5 3 3 9 SYSTEM CONTROL INSTRUCTIONS Privileged instructions trapPing instructions and instructions that use or modify the CCR provide system control operations All of these instructions cause the processor to flush the instruction pipeline Table 5 11 summarizes the instructions T...

Page 167: ...ged then execute returned operation word else trap as illegal instruction BGND none none If backgroundmode enabled then enter background mode else formaVvector offset SSP PC SSP SR SSP vector PC CHK ea On 16 32 If On 0 or On ea then CHK exception CHK2 ea Rn 8 16 32 If Rn lower bound or Rn upper bound then CHK exception ILLEGAL none none SSP 2 SSP vector offset SSP SSP 4 SSP PC SSP SSP 2 SSP SR SSP...

Page 168: ...00 1101 1110 1111 Test 1 0 C Z C Z C C Z Z V V N N N V N V N V N V N V Z N V Z Z N V N V There are four TBL instructions TBLS returns a signed rounded byte word or long word result TBLSN returns a signed unrounded byte word or long word result TBLU returns an unsigned rounded byte word or long word result TBLUN returns an unsigned unrounded byte word or long word result All four instructions suppo...

Page 169: ...e table consists of 257 word entries As shown in Figure 5 7 the function is linear within the range 32768 X 49152 Table entries within this range are as given in Table 5 13 5 30 Table 5 13 Standard Usage Entries Entry Number X Value YValue 128 32768 1311 162 41472 1659 163 41728 1669 164 41984 1679 165 42240 1690 192 49152 1966 These values are the end POints of the range All entries between these...

Page 170: ... 8 the data from Example 1 has been compressed by limiting the maximum value of the independent variable Instead of the range 0 S X 65535 X is limited to 0 S X S 1023 The table has been compressed to only five entries but up to 256 levels of interpolation are allowed between entries MOTOROLA y 256 512 786 1024 INDEPENDENT VARIABLf Figure 5 8 Table Example 2 NOTE Extreme table compression with many...

Page 171: ... the table instruction calculates dependent variable Y Y 1331 142 1966 1311 256 1674 The function chosen for Examples 1 and 2 is linear between data pOints If another function had been been used interpolated values might not have been identical 5 3 4 3 TABLE EXAMPLE 3 8 BIT INDEPENDENT VARIABLE This example shows how to use a table instruction within an interpolation subroutine Independent variabl...

Page 172: ...68 48 4 1024 64 5 1280 80 6 1536 96 7 1792 112 8 2048 128 9 2304 112 10 2560 96 11 2816 80 12 3072 64 13 3328 48 14 3584 32 15 3840 16 16 4096 0 4096 The first column is the value passed to the subroutine the second column is the value expected by the table instruction and the third column is the result returned by the subroutine MOTOROLA MC68340 USER S MANUAL 5 33 ...

Page 173: ...shift fills the least significant digits of the word with zeros the interpolation fraction can only have one of 16 values After the shift operation Ox contains the following value 31 16 15 NOT USED 10000 1 0 1 1 Execution of the table instruction using the new value in Ox yields Table Entry Offset Ox 8 15 OB 11 Interpolation Fraction Ox 0 7 00 208 Thus Y is calculated as follows Y 80 208 64 80 125...

Page 174: ...cording to the same algorithm Rounding yields 00100000 0111 0000 0011 1111 0111 0000 00000001 0111 0000 0110 0001 0101 0000 0110 0001 The second result is preferred The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results LO TBLSN B ea Ox TBLSN B ea Ox TBLSN B ea OI AOO L OX Om Long addition avoi...

Page 175: ...mmodate the scaled fractional results of the 20 TBL 5 3 5 Nested Subroutine Calls The LINK instruction pushes an address onto the stack saves the stack address at which the address is stored and reserves an area of the stack for use Using this instruction in a series of subroutine calls will generate a linked list of stack frames The UNlK instruction removes a stack frame from the end of the list ...

Page 176: ...halted condition should not be confused with the stopped condition After the processor executes a STOP or LPSTOP instruction execution of instructions can resume when a trace interrupt or reset exception occurs 5 4 2 Privilege Levels T p r tftM _ _ __ L _ _______________ a _ __ a _ _ aL __ _It _ _ r I v v 1 VI IVI VI u n vo UI access user or supervisor Supervisor level is more privileged than user...

Page 177: ...he S bit is set to enable supervisory access Execution continues at supervisor privilege level until exception processing is complete To return to user access level a system routine must execute one of the following instructions MOVE to SR ANDI to SR EORI to SR ORI to SR or RTE These instructions execute only at supervisor privilege level and can modify the S bit of the SA After these instructions...

Page 178: ...on 6 24 018 SO CHK CHK2 Instructions 7 28 01C SO TRAPcc TRAPV Instructions 8 32 020 SO Privilege Violation 9 36 024 SO Trace 10 40 028 SO Line 1010 Emulator 11 44 02C SO Line 1111 Emulator 12 48 030 SO Hardware Breakpoint 13 52 034 SO Reserved for Coprocessor Protocol Violation 14 56 038 SO Format Error 15 60 03C SO Unin ialized Interrupt 16 23 64 040 SO Unassigned Reserved 92 05C 24 96 060 SO Spu...

Page 179: ...resses word or long word operand accesses from odd addresses and privilege violations also cause internal exceptions Sources of external exception include interrupts breakpoints bus errors and reset requests Interrupts are peripheral device requests for processor action Breakpoints are used to support development equipment Bus error and reset are used for access control and processor restart 5 5 1...

Page 180: ...igure 5 10 Although some formats are peculiar to a particular M68000 Family processor format 0000 is always legal and always indicates that only the first four words of a frame are present See 5 5 4 CPU32 Stack Frames for a complete discussion of exception stack frames 15 SP Q i STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW FORMAT I VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION _ _ _ ...

Page 181: ...lete As a general rule when simultaneous exceptions occur the handler routines for lower priority exceptions are executed before the handler routines for higher priority exceptions For example consider the arrival of an interrupt during execution of a TRAP instruction while tracing is enabled Trap exception processing 2 is done first followed immediately by exception processing for the trace 4 1 a...

Page 182: ...the reset exception vector 6 Loads the first long word of the vector into the interrupt SP 7 Loads the second long word of the vector into the PC 8 Fetches and initiates decode of the first instruction to be executed Figure 5 11 is a flowchart of the reset exception After initial instruction prefetches normal program execution begins at the address in the PC The reset exception does not save the v...

Page 183: ...TRY II 0 T1 7 12 10 0 VBR OTHERWISE SP VECTOR O OTHERWISE pc VECTOR 1 OTHERWISE BEGIN INSTRUCTION d USERRORI ADDRESS ERROR DOUBLE BUS FAULT Figure 5 11 Reset Operation Flowchart MC68340 USER S MANUAL MOTOROLA ...

Page 184: ...ormat organizations are utilized to provide additional information regarding the nature of the fault First any register altered by a faulted instruction EA calculation is restored to its initial value Then a special status word SSW is placed on the stack The SSW contains specific information about the aborted access size type of access read or write bus cycle ty A nd function code Finallv fault ad...

Page 185: ... trap exception will be processed first then the trace exception The vector number for the TRAP instruction is internally generated part of the number comes from the instruction itself The trap vector number PC value and a copy of the SR are saved on the supervisor stack The saved PC value is the address of the instruction that follows the instruction that generated the trap For all instruction tr...

Page 186: ...tion in the stack frame If the format of the control data is improper the processor generates a format error exception This exception saves a four word format exception frame and then vectors through vector table entry number 14 The stacked PC is the address of the RTE instruction that discovered the format error 5 5 2 8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS An instruction is illegal if it ___ a _...

Page 187: ... saved on the supervisor stack with the saved value of the PC being the address of the illegal or unimplemented instruction 5 5 2 9 PRIVILEGE VIOLATIONS To provide system security certain instructions can be executed only at the supervisor access level An attempt to execute one of these instructions at the user level will cause an exception The privileged exceptions are as follows AND Immediate to...

Page 188: ...is illegal unimplemented or privileged an exception is not generated I ___ _ I_I __ __ 1 __ lA l r l fnr ILlig 1 g QIIL Llilly 1 IV I I _11 11 ___ _ _ ___ __ _ I __ v_w_ _ ____ _ future use Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction Exception processing follows the regular sequence tracing is disable...

Page 189: ...ctors within each exception vector table Careful use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the processor Interrupt recognition and subsequent processing are based on internal interrupt request signals IRQ7 IRQ1 and the current priority set in SR priority mask 12 10 Interrupt request level zero IRQ7 IRQ1 negated indicate...

Page 190: ...ripherals provide for programmable interrupt vector numbers to be used in the system interrupt request acknowledge mechanism If the vector number is not initialized after reset and if the peripheral must acknowledge an interrupt request the peripheral should return the uninitialized interrupt vector number 15 AA Ar tinn Bm O Aratinn for detailed information on interruot acknowledae cvcles 5 5 2 12...

Page 191: ...e remains intact so that it may be examined and repaired by an exception handler or used by a different type of processor e g MC68010 MC68020 or future M68000 processor in a multiprocessor system 5 5 3 Fault Recovery There are four phases of recovery from a fault recognizing the fault saving the processor state repairing the fault if possible and restoring the processor state Saving and restoring ...

Page 192: ...eption was processed Pending breakpoint status is stacked regardless of the type of bus error exception 0 Breakpoint not pending 1 Breakpoint pending BO indicates that a breakpoint exception was pending on channel 0 internal breakpoint source when the bus error exception was processed Pending breakpoint status is stacked regardless of the type of bus error exception o Breakpoint not pending 1 Brea...

Page 193: ... The function code for the faulted cycle is stacked in the FUNC field of the SSW which is a copy of FC2 FCO for the faulted bus cycle This field is reloaded into the bus controller if the RR bit is set during unstacking All unused bits are stacked as zeros and are ignored during unstacking Further discussion of the SSW is included in 5 5 3 1 Types of Faults 5 5 3 1 TYPES OF FAULTS An efficient imp...

Page 194: ...considered released All type II faults cause an immediate exception that aborts the current instruction Any registers that were altered as the result of an EA calculation Le postincrement or predecrement are restored prior to processing the bus cycle fault The SSW for faults in this category contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I 0 I 0 I 0 I 0 I B1 I BO I 0 I RM I...

Page 195: ...et to indicate that the write should be rerun upon return from the exception handler The remainder of the stack frame contains sufficient information to continue MOVEM with operand transfer following a faulted transfer The address of the next operand to be transferred incremented or decremented by operand size is stored in the faulted address location 08 The stacked transfer counter is set to 16 m...

Page 196: ...erand is rewritten the RR bit must be cleared Failure to clear the RR bit can cause the RTE instruction to rerun the bus cycle Following rewrite it is not necessary to adjust the PC or other stack contents before executing RTE 5 5 3 2 2 Type I Completing Released Writes via RTE An exception handler can use the RTE instruction to complete a faulted bus cycle When RTE executes the fault address data...

Page 197: ...6 to obtain the number of operands transferred Scan the mask using this count value Each time a set bit is found clear it and decrement the counter When the count is zero the mask is ready for use Adjust the operand address If the predecrementaddressing mode is in effect subtract the operand size from the stacked value otherwise add the operand size to the stacked value B Rerun Instruction Scan th...

Page 198: ... contents of the remainder of the frame A fault address corresponding to the vector specified in the stacked formaUvector word indicates that the processor could not obtain the address of the exception handler A bus error exception handler should execute RTE after correcting a fault RTE restores the internal machine state fetches the address of the original exception handler recreates 1 1 ___ _ __...

Page 199: ...s of the next instruction to be executed SP 02 06 08 15 o STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW o I 0 I 1 I 0 I VECTOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW Figure 5 13 Format 2 Six Word Stack Frame Hardware breakpoints also utilize this format The faulted instruction PC value is the address of t...

Page 200: ...ored unless the MV bit in the stacked SSW is set If the MV bit is set the least significant byte of the internal register is reloaded into the MOVEM transfer counter during RTE execution For faults occurring during normal instruction execution both prefetches and non MOVEM operand accesses SSW TP MV 00 Stack frame format is shown in Figure 5 15 Faults that occur during the operand portion of the M...

Page 201: ...UNT REGISTER SPECIAL STATUS WORD Figure 5 15 Format C BERR Stack for Prefetches and Operands SP 02 06 08 OC 10 14 16 15 o STATUS REGISTER RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW 1 I 1 I o I 0 I VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW DBUF HIGH DBUF LOW CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW INTERNAL TRANSFER COUNT REGISTER o I...

Page 202: ...bugger program to monitor execution of a program under test See 5 5 2 10 Tracing for more information Dro nl in 1 II rlll til n An orrtl d lt n inC ori C ftuI ar o h o Lrn jnt intn t r ot I nno tn r indicate when a breakpoint occurs On the MC68010 MC68020 MC68030 and CPU32 this function is provided via illegal instructions 4848 484F that serve as breakpoint instructions See 5 5 2 5 Software Breakp...

Page 203: ...plified The BSA monitors target processor operation and the on chip debugger controls the operating environment Emulation is much closer to target hardware thus many interfacing problems Le limitations on high frequency operation AC and DC parametric mismatches and restrictions on cable length are minimized TARGET SYSTEM L TARGET BUS STATE MeU ANALYZER Figure 5 19 Bus State Analyzer Configuration ...

Page 204: ... block diagram BOM can be initiated in several ways by externally generated breakpoints by internal peripheral breakpoints by the background instruction BGNO or by catastrophic exception conditions While in BOM the CPU32 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated high speed SPI type serial command interface MICROCODE I EXECUTION U...

Page 205: ...kground Illegal Instruction BKPT Instruction Opcode Subst utionl Opcode Subst utionl Illegal Instruction Illegal Instruction 5 6 2 2 1 External BKPT Signal Once enabled BOM is initiated whenever assertion of BKPT is acknowledged If BOM is disabled a breakpoint exception vector OC is acknowledged The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle dat...

Page 206: ...is complete Result operands are loaded into the output shift register to be shifted out as the next command is read This orocess is reoeated for each command until thA CPt J returns to normal operating mode 5 6 2 5 80M REGISTERS 80M processing uses three special purpose registers to track program context during development A description of each register follows 5 6 2 5 1 Fault Address Register FAR...

Page 207: ... OUT 17BITS DISABLE SHIFT CLOCK READ RESULT REGISTER FRESULTS YES NOTREADY NO CONTINUE Figure 5 21 80M Command Execution Flowchart 5 6 2 6 RETURNING FROM 80M BOM is terminated when a resume execution GO or call user code CALL command is received Both GO and CALL flush the instruction pipeline and prefetch instructions from the location pointed to by the RPC The return PC and the memory space refer...

Page 208: ...atus of CPU generated messages as shown in Table 5 21 Table 5 21 CPU Generated Message Encoding Encoding Data Message Type 0 xxxx Valid Data Transfer 0 FFFF Command Complete Status OK 1 0000 Not Ready with Response Come Again I 1 I 0001 I Ct Mn It IIllII IICU Uii I t Cil I 1 FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16 The current implemen...

Page 209: ...after the synchronized DSCLK has been seen internally the updated counter value is checked If the counter has reached zero the receive data latch is updated from the input shift register At this same time the output shift register is reloaded with the not ready come again response Once the receive data latch has been loaded the CPU is released to act on the new data Response data overwrites the no...

Page 210: ...ster of the serial data link must supply the serial clock However normal and BOM operations could interact if the clock generator is not properly designed Breakpoint requests are made by asserting BKPT to the low state in either of two ways The primary method is to assert BKPT during a single bus cycle for which an exception is desired Another method is to assert BKPT then continue to assert it un...

Page 211: ...G _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ FREEZE L I Figure 5 25 BKPT Timing for Forcing BDM Figure 5 26 represents a sample circuit providing for both BKPT assertion methods As the name implies FORCE_BGNO is used to force a transition into BOM by the assertion of BKPT FORCE_BGNO can be a short pulse or can remain asserted until FREEZE is asserted Once asserted the set reset latch holds BKP...

Page 212: ... the commands This 6 bit field provides for a maximum of 64 unique commands Am Field The R W field specifies the direction of operand transfer When the bit is set the transfer is from CPU to development system When the bit is cleared data is written to the CPU or to memory from the development system Operand Size For sized operations this field specifies the operand data size All addresses are exp...

Page 213: ...nemonic in this example read memory location During the same cycle the CPU responds with either the lowest order results of the previous command or with a command complete status if no results were required During the second cycle the development system supplies the high order 16 bits of the memory address The CPU returns a not ready response unless the received command was decoded as unimplemente...

Page 214: ...S FROM PREVIOUS COMMAND RESPONSES FROM THE CPU NONSERIAL RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED SEQUENCE TAKEN IF BUS ERROR OR ADDRESS ERROR OCCURS ON MEMORY ACCESS HIGH AND LOW ORDER 16 BITS OF RESULT Figure 5 27 Command Sequence Diagram 5 6 2 8 3 Command Set Summary The BDM command set is summarized in Table 5 23 Subsequent paragraphs contain detailed deSCriptions of each...

Page 215: ...l READ is executed to set up the starting address of the block and to retrieve the first result Subsequent operands are retrieved with the DUMP command Fill Memory Block FILL Used in conjunction with the WRITE command to fill large blocks of memory An initial WRITE is executed to set up the starting address of the block and to supply the first operand Subsequent operands are written with the FILL ...

Page 216: ...and Data Long word data is written into the specified address or data register The data is supplied most significant word first Result Data Command complete status OFFFF is returned when register write is complete 5 6 2 8 6 Read System Register RSREG The specified system control register is read All rQ ic tQrc th t n hI rl rI in C lJOflrvic or mode can be read in 80M Several internal temporary reg...

Page 217: ... Code Register DFC 1111 Temporary Register A ATEMP 1000 Fault Address Register FAR 1001 Vector Base Register VBR 1010 5 6 2 8 7 Write System Register WSREG Operand data is written into the specified system control register All registers that can be written in supervisor mode can be written in 80M Several internal temporary registers are also accessible Command Format 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 218: ...o I 0 I 0 o I Command Sequence Operand Data The single operand is the long word address of the requested memory location Result Data The requested data is returned as either a word or long word Byte data is returned in the least significant byte of a word result with the upper byte cleared Word results return 16 bits of significant data long word results return 32 bits A successful read operation ...

Page 219: ...rand Data Two operands are required for this instruction The first operand is a long word absolute address that specifies a location to which the operand data is to be written The second operand is the data Byte data is transmitted as a 16 bit word justified in the least significant byte 16 and 32 bit operands are transmitted as 16 and 32 bits respectively Result Data Successful write operations r...

Page 220: ... updated address back in the temporary register NOTE The DUMP command does notcheck for a valid address in the temporary register DUMP is a valid command only when preceded by another DUMP or by a READ command Otherwise the results are undefined The NOP command can be used for intercommand padding without corrupting the address pOinter The size field is examined each time a DUMP command is given a...

Page 221: ...th the FILL command The initial address is incremented by the operand size 1 2 or 4 and is saved in a temporary register Subsequent FILL commands use this address increment it by the current operand size and store the updated address back in the temporary register NOTE The FILL command does not check for a valid address in the temporary register FILL is a valid command only when preceded by anothe...

Page 222: ...d Prefetching begins at the return PC and current privilege level If either the PC or SR is altered during BOM the updated value of these registers is used when prefetching commences NOTE The processor exits BOM when a bus error or address error occurs on the first instruction prefetch from the new PC the error is trapped as a normal mode exception The stacked value of the current PC may not be va...

Page 223: ... execution begins NOTE If a bus error or address error occurs during return address stacking the CPU returns an error status via the serial interface and remains in BOM If a bus error or address error occurs on the first instruction prefetch from the new PC the processor exits BOM and the error is trapped as a normal mode exception The stacked value of the current PC may not be valid in this case ...

Page 224: ...O CHKSTAT TBA OUTPUT 3 00 Move serial status to DO Loop until condition true Transmit character Check for TxEMP flag BDM and the CALL command can be used to patch the code as follows 1 Breakpoint user program at CHKSTAT 2 Enter BDM 3 Execute CALL command to MISSING 4 Exit BDM 5 Execute MISSING code 6 Return to user program 5 6 2 8 14 Reset Peripherals RST RST asserts RESET for 512 clock cycles The...

Page 225: ...e serial shifter after negation of RESET 5 6 2 8 15 No Operation NOP NOP performs no operation and may be used as a null command where required Command Format 15 14 13 12 11 0 I 0 I 0 I 0 0 Command Sequence Operand Data None Result Data 10 9 0 I 0 I 8 7 0 0 I NEXTCMD CMD COMPLETE xxx ILLEGAL 6 5 4 3 2 o 0 0 o The command complete response OFFFF is returned during the next shift operation 5 86 MC68...

Page 226: ...signal a pipeline flush with associated prefetch followed immediately by a second prefetch That is IFETCH remains asserted for three clocks two clocks indicating the flush fetch and a third clock signaling the second fetch These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of CLKOUT which follow the AS DS during show cycles falling edge Three clo...

Page 227: ...UCTION EXTENSION START WORD USED INSTRUCTIONS START Figure 5 29 Instruction Pipeline Timing Diagram IPIPE should be sampled on the falling edge of the clock The assertion of IPIPE for a single cycle after one or more cycles of negation indicates use of the data in IRB advance of IRA into IRB Assertion for two clock cycles indicates that a new instruction has started IRB IRC and IRA IRB transfers h...

Page 228: ...xt within which the instruction is executing 5 7 1 1 MICROSEQUENCER The microsequencer either executes microinstructions or awaits completion of accesses necessary to continue microcode execution The microsequencer supervises the bus controller instruction execution and internal processor operations such as calculation of EA and setting of condition codes It also initiates instruction word prefetc...

Page 229: ...ontroller receives an initial request from the microsequencer to initiate prefetching at a given address Subsequent prefetches are initiated by the prefetch controller whenever a pipeline stage is invalidated either through instruction completion or through use of extension words Prefetch occurs as soon as the bus is free of operand accesses previously requested by the microsequencer Additional st...

Page 230: ...port Long operands are accessed in two bus cycles most significant word first The instruction pipeline is capable of recognizing instructions that cause a change of flow It informs the bus controller when a change of flow is imminent and the bus controller refrains from starting prefetches that would be discarded due to the change of flow 5 7 1 4 INSTRUCTION EXECUTION OVERLAP Overlap is the time m...

Page 231: ...es due to slow external memory must be added to the access time for each bus cycle A typical application has a mixture of bus speeds program execution from an off chip ROM accesses to on chip peripherals storage of variables in slow off chip RAM and accesses to external peripherals with speeds ranging from moderate to very slow To arrive at an accurate instruction time calculation each bus access ...

Page 232: ...o TOr me Insuuctlon IS me neaa TOr me CI am i U1t1 uvtlli iii li iii lUI lill instruction is the tail for the operation Therefore the actual equation for execution time becomes COP1 min TOP1 HEA2 CEA 2 min TEA2 HOP2 COP2 min TOP2 HEA3 Every instruction must prefetch to replace itself in the instruction pipe Usually these prefetches occur during or after an instruction A prefetch is permitted to be...

Page 233: ... 4 0 THEN NEW_CYCLE OLD_CYCLE NEW_CLOCK 2 NEW_CLOCK 4 ELSE NEW_CYCLE OLD_CYCLE NEW _CLOCK 2 where NEW_TAIUNEW_CYCLE is the adjusted tail cycle at the slower speed OLD_TAIUOLD_CYCLE is the value listed in the instruction timing tables NEW_CLOCK is the number of clocks per cycle at the slower speed Note that many instructions listed as having negative tails are change of flow instructions and that t...

Page 234: ...CTIONS Example 2 shows what happens when a branch instruction is executed for both the taken and not taken cases see Figures 5 34 and 5 35 The instruction stream is for a simple limit check with the variable already in a data register _ Instructions CLOCK BUS CONmOLLER INSTRUCTION CONmOLLER EXECUTION TIME MOTOROLA 2 3 MOVEa 7 01 CMP L 01 00 BLE B NEXT MOVE L 01 AO 4 6 7 9 0 2 3 Figure 5 34 Example...

Page 235: ...s per access Instruction three is at the branch destination Although the CPU32 has a two word instruction pipeline internal delay causes minimum branch instruction time to be three bus cycles The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus on a slower bus there is no extra time for the third word CLOCK BUS CONmOLlER tlSTRUCTION CONm...

Page 236: ...l The number of cycles an instruction uses to complete a write Cycles Four numbers per entry three contained in parentheses The outer number is the minimum number of cycles required for the instruction to complete Numbers within the parentheses represent tne numoer aT ous accesses penormeci DY lil instruction The first number is the number of operand read accesses performed by the instruction The ...

Page 237: ...on has a head of zero and a tail of four because it is a long write The LSL instruction has a head of four The trailing write from the MOVE overlaps the LSL head completely Thus the two instruction sequence has a head of zero and a tail of zero and a total execution of 8 rather than 12 clocks General observations regarding calculation of execution time are as follows Any time the number of bus cyc...

Page 238: ... 1 2 4 An Xm Sz x Sc 4 2 8 Xl1 0 1 2 3 4 I J A_ _ J n A v_ 1 d32 An or d32 PC 1 5 9 XI3 O 1 3 4 dI6 An Xm or dI6 PC Xm 2 2 8 XI2 0 1 3 4 d32 An Xm or d32 PC Xm 1 3 9 XI3 0 1 3 4 d16 An Xm Sz x Sc or dlS PC Xm Sz x Sc 2 2 8 XI2 0 1 2 3 4 d32 An Xm Sz x Sc or d320PC Xm Sz x Sc 1 3 9 XI3 0 1 2 3 4 x There is one bus cycle for byte and word operands and two bus cycles for long word operands For long w...

Page 239: ... 1 3 7 0 3 0 1 4 An 1 0 4 0 1 0 4 Xm Szx Sc 4 0 6 0 1 0 2 4 An Xm Sz x Sc 4 0 6 0 1 0 2 4 dI6 An or dI6 PC 1 1 5 0 2 0 1 3 4 d32 An or d32 PC 1 3 7 0 3 0 1 3 4 dI6 An Xm or d16 PC Xm 2 0 6 0 2 0 3 4 d32 An Xm or d32 PC Xm 1 1 7 0 3 0 1 3 4 dI6 An Xm Sz x Sc or dlS PC Xm Sz x Sc 2 0 6 0 2 0 2 3 4 d32 An Xm Sz x Sc or d32 PC Xm Sz x Sc 1 1 7 0 3 0 1 2 3 4 x There IS one bus cycle for byte and word o...

Page 240: ... X MOVE FEA An 2 2 6 0 1 X MOVE FEA An 2 2 6 0 1 X MOVE CEA 2 2 6 0 11x MOVE CEA FEA 2 2 6 0 1 X x There is one bus CYcle for byte and word ooarands and two bus C I IA fn Innn_wn tI operandS or long word bus cycles add two clocks to the tail and to the number of cycles An fetch EA time must be added for this instruction FEA CEA OPER NOTE For instructions not explicitly listed use the MOVE CEA FEA ...

Page 241: ... cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles Each bus cycle may take up to four clocks without increasing total execution time Cr Control registers USP VBR SFC and OFC n Number of registers to transfer RL Register List Maximum time certain data or mode combinations may execute faster NOTE The MOVES instruction has an additional save step whic...

Page 242: ... 0 SUB On FEA 0 3 5 0 1Ix CMP A Rn Rm 0 0 2 0 1 0 CMP A FEA Rn 0 0 2 0 1 0 CMP2 Save FEA Rn 1 1 3 0 1 0 CMP2 Op FEA Rn 2 0 16 18 Xll 0 MUL su W FEA On 0 0 26 0 1 0 MUL su L Save FEA On 1 1 3 0 1 0 lAlllI III ILr A nl A MUL su L Op FEA On OI 2 0 46 0 1 0 OIVU W FEA On 0 0 32 01110 OIVS W FEA On 0 0 42 011 0 OIVU L Save FEA On 1 1 3 0 1 0 OIVU L Op FEA On 2 0 46 011 0 OIVS L Save FEA On 1 1 3 0 110 ...

Page 243: ...certain data or mode combinations may execute faster su The execution time is identical for signed or unsigned operands These instructions have an additional save operation that other instructions do not have To calculate total instruction time calculate save ea and operation execution times then combine in the order shown using equations in 5 7 1 6 Instruction Execution Time Calculations A save o...

Page 244: ...ck cycle number All timing data assumes two clock reads and writes Instruction Head Tall Cycles MOVEQ Dn 0 0 2 0 1 0 ADDQ An 0 0 2 0 1 0 ADDQ FEA 0 3 5 0 1 X SUBQ An 0 0 2 0 1 0 SUBQ FEA 0 3 5 0 1 X ADDI An 0 0 2 0 1 0 ADDI FEA 0 3 5 0 1 X ANDI An 0 0 2 0 1 0 ANDI FEA 0 3 5 0 1 x EOAI An 0 0 2 0 1 0 EOAI FEA 0 3 5 0 1 X OAI An 0 0 2 0 1 0 OAI FEA 0 3 5 0 1 x SUBI An 0 0 2 0 1 0 SUBI FEA 0 3 5 0 1 ...

Page 245: ...n time for these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tall Cycles ABCD On Om 2 0 4 011 0 ABCD An Am 2 2 12 211 1 SBCD Dn Dm 2 0 4 0 1 0 SBCD An Am 2 2 12 2 1 1 ADDX Dn Dm 0 0 2 0 1 0 ADDX An Am 2 2 10 2 111 SUBX On...

Page 246: ...ck reads and writes Instruction Head Tall Cycles CLR On 0 0 2 0 1 0 CLR CEA 0 2 4 0 1 x NEG On 0 0 2 0 1 0 NEG FEA 0 3 5 0 1 X NEGX On 0 0 2 0 1 0 NEGX FEA 0 3 5 0 1 X NOT On 0 0 2 0 1 0 NOT FEA 0 3 5 0 1 X EXT On 0 0 2 0 1 0 NBCO On 2 0 4 0 1 0 NBCO FEA 0 2 6 0 1 1 Sec On 2 0 4 0 1 0 Sec CEA 2 2 6 0 1 1 TAS On 4 0 6 0 1 0 TAS CEA 1 0 10 0 111 TST FEA 0 0 2 0 1 0 X There is one bus cycle for byte ...

Page 247: ...On Om ROd Om ROd FEA ROXd On Om ROXd Om ROXd FEA d a Olrectlon left or right NOTES Head TaU Cycles 2 0 0 1 0 4 0 6 0 1 0 0 2 6 011 1 2 0 0 1 0 4 0 6 011 0 0 2 6 0 1 1 2 0 0 1 0 4 0 6 011 0 0 2 6 0 1 1 2 0 0 1 0 2 0 0 1 0 0 2 6 0 1 1 1 Head and cycle times can be derived from the following table or calculated as follows Max 3 n 4 mod n 4 mod n 4 mod n 4 1 2 6 2 Head and cycle times are calculated a...

Page 248: ... number All timing data assumes two clock reads and writes Instruction Head Tall Cycles BCHG On 2 0 6 01210 BCHG On Om 4 0 6 011 0 BCHG FEA 1 2 8 01211 BCHG On FEA 2 2 8 0 111 BCLA On 2 0 6 01210 BCLA On Om 4 0 6 011 0 BCLA FEA 1 2 8 01211 BCLA On FEA 2 2 8 0 1 1 BSET On 2 0 6 01210 BSET On Om 4 0 6 0 1 0 BSET FEA 1 2 8 01211 BSET On FEA 2 2 8 011 1 BTST On 2 0 4 01210 BTST On Om 2 0 4 0 1 0 BTST ...

Page 249: ...umber of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tall Cycles Bcc taken 2 2 8 01210 Bcc B not taken 2 0 4 011 0 Bcc W not taken 0 0 4 01210 Bcc L not taken 0 0 6 0 3 1 OBcc T not taken 1 1 4 01210 OBcc F 1 not taken 2 0 6 01210 OBcc F not 1 taken 6 2 ...

Page 250: ...0 CHK FEA On ex 2 2 42 212 6 CHK2 Save FEA On no ex 1 1 3 0 110 CHK2 Op FEA On no ex 2 0 18 XlO 0 CHK2 Save FEA On ex 1 1 3 0 110 CHK2 Op FEA On ex 2 2 S2 X 21116 JMP CEA 0 2 6 012 0 JSR CEA 3 2 13 012 2 LEA CEA An 0 0 2 0 110 LlNK W An 2 0 10 01212 LlNK L An 0 0 10 01312 NOP 0 0 2 0 110 PEA CEA 0 0 8 0 112 RTD 1 2 12 21210 RTR 1 2 14 3 210 RTS 1 2 12 2 210 UNLK An 1 0 9 21110 x There is one bus c...

Page 251: ...25 0 3 1 Divide by Zero 0 2 36 21216 Trace 0 2 36 2 216 TRAP 4 2 29 2 214 ILLEGAL 0 2 25 2 214 A line 0 2 25 21214 F line First word illegal 0 2 25 21214 F line Second word illegal ea Rn 1 2 31 2 3 4 F line Second word illegal ea Rn Save 1 1 3 0 1 0 F line Second word illegal ea Rn Op 4 2 29 21214 Privileged 0 2 25 21214 TRAPcc trap 2 2 38 2 216 TRAPcc no trap 2 0 4 0 1 0 TRAPcc W trap 2 2 38 2 21...

Page 252: ...ses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tall Cycles BERR on instruction 0 2 58 212112 BERR on exception 0 2 48 212112 RTE four word frame 1 2 24 41210 RTE six word frame 1 2 26 41210 RTE BERR on instruction 1 2 50 121121V RTE BERR on four word frame 1 2 66 101214 RTE BERR on six word f...

Page 253: ...5 114 MC68340 USER S MANUAL MOTOROLA ...

Page 254: ...Fully Programmable DMA Channels Single Address Transfers with 32 Bit Address and 32 Bit Data Capability Dual Address Transfers with 32 Bit Address and 16 Bit Data Capability Two 32 Bit Transfer Counters Four 32 Bit Address Pointers That Can Increment or Remain Constant Operand Packing and Unpacking for Dual Address Transfers Supports All Bus Termination Modes Provides Two Clock Cycle Internal Modu...

Page 255: ...l address transfers In single address mode a channel supports 32 bits of address and 32 bits of data Only an external request can be used to start a transfer in the single address mode The DMA provides address and control signals during a single address transfer The requesting device either sends or receives data to or from the specified address see Figure 6 2 In dual address mode a channel suppor...

Page 256: ...r G t MEMORY I PERIPHERAL I G __ I l Figure 6 2 Single Address Transfers H MEMORY G t MEMORY Figure 6 3 Dual Address Transfer MOTOROLA MC68340 USER S MANUAL 6 3 ...

Page 257: ...request 6 2 3 DMA Done DONEx This active low bidirectional signal is asserted by the DMA or a peripheral device during any DMA bus cycle to indicate that the last data transfer is being performed DONEx is an active input in any mode As an output DONEx is only active in external request mode An external pullup resistor is required even if operating only in the internal request mode 6 3 TRANSFER REQ...

Page 258: ...can be for either single or dual address transfers 6 3 2 1 EXTERNAL BURST MODE For external devices that require very high data transfer rates the burst request mode allows the DMA channel to use all of the bus bandwidth under control of the external device In burst mode the DREOx input to the DMA is level sensitive and is sampled at certain pOints to determine when a valid request u _ _ __ Th_ __...

Page 259: ...odule DMAMODULE SERiAl MODULE DREOl TxRDYA DRE02 RxRDYA Figure 6 4 DMA External Connections to Serial Module For serial receive the DMA reads data from the serial receive buffer RS register when the serial module has filled the buffer on input and writes data to memory For serial transmit the DMA reads data from memory and writes data to the serial transmit buffer TS register Only dual address mod...

Page 260: ... burst transfer mode or cycle steal mode See 6 7 Register Description for more information If external 32 bit devices and a 32 bit bus are used with the MC68340 the DMA can control 32 bit transfers between devices that use the 32 bit bus in single address mode only External logic is required to complete a 32 bit long word transfer If both byte and word devices are used on an external bus then an e...

Page 261: ...Timing 10 generate more than one DMA request 2 end DMA control signals ere esserted in the source read DMA cycle 3 mIEii must be asserted while is esserted end meet the setup and hold times for more than one DMA transfer 10 be recognized Figure 6 5 Single Address Read Timing External Burst MC68340 USER S MANUAL MOTOROLA ...

Page 262: ... DMAREAD DONEx OUTPUT NOTE 1 DREax must be active for two conseCi ve clocks for a D est to be recognized __ 2 To cause another DMA lransfer DREe x is asserted after DACKx is asserted and before DACKx is negated 3 DACKx and DONEx DMA control sign lis are asserted in he source read DMA cycle Figure 6 5 Single Address Read Timing Cycle Steal I ...

Page 263: ...re asserted in the destination write cycle See Figures 6 7 and 6 8 for timing diagrams of single address write for external burst and cycle steal modes 6 10 CPU CYCLE OMAWRITE OMAWRITE so S2 54 so S2 54 so S2 CLKOUT A31 AO FC3 fCO SlZl 51ZO 015 00 O INPUT OON r OUTPUT NOTE 1 Timing to generate more than one DMA raquest 54 CPU CYClE so 2 DACKx and DONEx DMA conlrQ igru ls are asserted in the source...

Page 264: ...DMAWRIlE CPU CYClE 1 OREOx must be active for two conseCUtil clocks for a O est to be recognized __ DMAWRIlE 2 To cause another OMA transfer OREQx asserted after OACKx is asserted and before OACKx is negated 3 OACKx and OONEx OMA control signal are asserted in the destination write OMA cycle Figure 6 s Single Address Write Timing Cycle Steal I ...

Page 265: ...es may be used See 6 7 Register Description for more information The dual address transfers can be started by either the internal request mode or by an external device using the DREQx input signal When the external device uses DREQx the channel can be programmed to operate in either burst transfer mode or cycle steal mode 6 4 2 1 DUAL ADDRESS READ During the dual address read cycle the DMA reads d...

Page 266: ...one DMA transfer 2 DACKx and DONEx DMA control signals are asl arted in the source read DMA cycle 3 DREQx must be assaned while DACKx is assam and meet the setup and hold times for more than one DMA transfer to be recognized 4 DONEx Qnput can be assened in either the read f write DMA bus cycle to indicate that the next DMA transfer will be the last one Figure 6 9 Dual Addl ess Read Timing External...

Page 267: ...est to be recognized CPU CYCLE 2 To cause another DMA transfer the DREOx is asserted after DACKx is asserted and before DACKx is negated 3 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle 4 DONEx input can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one Figure 6 10 Dual Address Read Timing Cycle Steal So...

Page 268: ... increment and size information specified by the DAPI and DSIZE bits of the CCR and the byte transfer count register BTC is decremented by the number of bytes transferred If the BTC is equal to zero and there were no errors the CSR DONE bit is set and the DONEx signal for the DMA handshake is asserted The DMA control signals DACKx and DONEx are asserted in the destination write cycle when the dest...

Page 269: ...Ex OMA control signals are asserted in the destination write OMA cycle OMAWRITE CPU CYCLE 3 OREQx must be asserted while OACKx is asserted and meet the setup and hold times for more than one OMA transfer to be recognized 4 OONEx input can be asserted in either the read or write OMA bus cycle to indicate that the next OMA transfer will be the last one Figure 6 11 Dual Address Write TIming External ...

Page 270: ... request to be recognized __ 2 To cause another DMA transfer DREQx is assertli j after DACKx is asserted and before DACKx is negated 3 DACKx and OONEx DMA control signals are ass iI1ed in the destination write DMA cycle DMAREAD 4 OONEx Input can be asserted in either the read rwrite DMA bus cycle to indicate that the next DMA transfer will be the last one Figure 6 12 Dual Addres Write Timing Cycle...

Page 271: ...rnally or externally generated is recognized 2 Data Transfer After a channel is started it transfers one operand in response to each request until an entire data block is transferred 3 Channel Termination The channel can terminate by normal completion or from an error The channel status register CSR indicates the status of the operation 6 6 1 Channel Initialization and Startup Before starting a bl...

Page 272: ... request DREQx must be asserted before the channel requests the bus The DREQx input is ignored until the channel is started since the channel does not recognize transfer requests until it is active If any fields in the CCR are modified while the channel is active that change is effective immediately To avoid any problems with changing the setup for the DMA channel a zero should be written to the S...

Page 273: ...nel operation can be terminated for several reasons the BTC is decremented to zero a peripheral device asserts DONEx during an operand transfer the STR bit is cleared in the CCR a bus cycle is terminated with a bus error or a reset occurs 6 6 3 2 INTERRUPT OPERATION Interrupts can be generated by error termination of a bus cycle or by normal channel completion Specifically if the CCR interrupt err...

Page 274: ...0 01 1 0 GClUI IY v Figure 6 13 Fast Termination Option Cycle Steal If the fast termination option is used with external burst request mode Figure 6 14 an extra DMA cycle may result on every burst transfer Normally DREOx is negated when DACKX is returned In the burst mode with fast termination selected a new cycle starts even if DREOx is negated simultaneously with DACKx assertion MOTOROLA MC68340...

Page 275: ...mer s model register map of all registers in the DMA module Each channel has an independent set of registers For more information about a particular register refer to the individual register description The ADDRESS column indicates the offset of the register from the base address of the DMA channel The FC column designation of S indicates that register access is restricted to supervisor only A des...

Page 276: ...module base address register MBAR in the SIM40 The first number is the offset for channel 1 the second number is the offset for channel 2 The numbers above the register represent the bit position in the register The register contains the mnemonic for the bit The value of these bits after a hardware reset is shown below the register The access 0 I _ _ __ L _____ __ L_ 1 __ ___ _l L __ I _____ _ IIY...

Page 277: ...uting the LPSTOP instruction to reduce overall power consumption o The channel operates in normal mode NOTE The DMA module uses only one STP bit for both channels A read or write to either MCR accesses the same STP control bit FRZ1 FAZQ Freeze These bits determine the action taken when the FREEZE signal is asserted on the 1MB when the CPU32 has entered background debug mode The DMA module negates ...

Page 278: ...ently defined as supervisor only access i iiil I _ space and are only accessible from supervisor programs o The DMA channel registers defined as supervisor user reside in user data space and are accessible from either supervisor or user programs MAID Master Arbitration ID These bits establish bus arbitration priority level among modules that have the capability of becoming bus master For the MC683...

Page 279: ... an interrupt level field The interrupt level field contains the priority level of the interrupt for its associated channel The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQx signal The CPU32 uses this value to determine servicing priority See Section 5 CPU32 for more information INTV Interrupt Vector Bits Each module that can generate interrupts has an interrupt...

Page 280: ...ters an error on source read CSR BES bit is set destination write CSR BED bit is set or configuration for channel setup CSR CONF bit is set 0 Does not enable an IROx when the channel encounters an error on source read destination write or confiQuration for channel setup ECO External Control Option If request generation is programmed to be internal REO bits 00 this bit has no effect Single Address ...

Page 281: ...The SAR is not incremented during operand transfer The address that is written into the SAR points to a peripheral device and is used for the complete data transfer DAPI Destination Address Pointer Increment 1 The DAR is incremented by 1 2 or 4 after each transfer according to the source size The address that is written into the DAR points to a memory block and is incremented to complete the data ...

Page 282: ...operand transfer request Table 6 4 defines these bits Table 6 4 REQx Encoding Bns BI14 Definition 0 0 Internal Request at Programmable Rate 0 1 Reserved 1 0 External Request Burst Transfer Mode 1 1 External Request Cycle Steal RR RII RAnnwinth FiAln This field controls the percentage of 1024 clock periods of the 1MB that the DMA channel can use during internal requests only Table 6 5 defines these...

Page 283: ...this bit is set o The DMA transfer can be stopped by clearing this bit External Request Mode 1 Setting this bit allows the DMA to start the transfer when a DREQx input is received from an external device o The DMA transfer can be stopped by clearing this bit NOTE If any fields in the CCR are modified while the channel is active that change is effective immediately To avoid any problems with changi...

Page 284: ...ED Bus Error on Destination 1 The DMA channel has terminated with a bus error during the write bus cycle a The DMA channel has not terminated with a bus error during the write bus cycle This bit is cleared by writing a logic one or by a hardware reset Writing a zero has no effect CONF Configuration Error iUIIII lUIi tLIUII tlIIUI ItI iUIL i WlltllI tllLlltll Llltl o n UI Llltl LJ n iUIILi LIII i i...

Page 285: ...o specify the destination access to a certain address space type The destination function code bits are defined in Table 6 6 6 32 Table 6 6 Address Space Encoding Function Code Bits 3 2 1 0 Address Spaces 0 0 0 0 Reserved Motorola 0 0 0 1 User Data Space 0 0 1 0 User Program Space 0 0 1 1 Reserved User 0 1 0 0 Reserved Motorola 0 1 0 1 Supervisor Data Space 0 1 1 0 Supervisor Program Space 0 1 1 1...

Page 286: ...pending on the size of the operand and the memory starting address If the operand size is byte then the register is always incremented by 1 If the operand size is word and the starting address is even word aligned then the register is incremented by 2 If the operand size is long word and the address is even word alianed then the reoister is incremented bv 4 The SAR value must be aligned to an even...

Page 287: ... the starting address is even word aligned the register is incremented by 2 If the operand size is long word and the address is even word aligned the register is incremented by 4 The DAR value must be aligned to an even word boundary if the transfer size is word or long word otherwise the CSR CONF bit is set and the transfer does not occur When read this register always contains the next destinati...

Page 288: ...e next access If a bus error terminates the transfer this register contains the count for the next access that would have been run had the error not occurred 6 8 DATA PACKING The internal DHR is a 32 bit register that can serve as a buffer register for the data being transferred during dual address DMA cycles No address is specified since this register can not be addressed by the programmer The DH...

Page 289: ... data bus operation in single address mode SE bit Program the interrupt service mask to set the level below which interrupts are ignored during a DMA transfer ISM bits The channel will begin operation when the level of the CPU32 SR 12 10 bits is less than or equal to the level of the DMA ISM bits Select the access privilege for the supervisor user registers SUPV bit Program the master arbitration ...

Page 290: ...riting 7C into it The DMA cannot be started until the DONE BES BED CONF and BRKP bits are cleared _ Function Code Register FCR Encode the source function code for a read cycle or the destination function code for a write cycle Address Register SAR or DAR Write the source address for a read cycle or the destination address for a write cycle Byte Transfer Counter BTC Encode the number of bytes to be...

Page 291: ...Code The following are examples of configuration sequences for a DMA channel in single and dual addressing modes MC68340 basic DMA channel register initialization example code This code is used to initialize the 68340 s internal DMA channel registers providing basic functions for operation The code sets up channel 1 for external burst request generation single address mode long word size transfers...

Page 292: ...M bits for channel startup Supervisor user reg unrestricted MAID field at 7 IARB priority at 1 MOVEW 1271 AO Clear channel control reg Clear STR start bit to prevent the channel from starting a transfer early CLR W DMACCR1 AO Initialize interrupt reg Interrupt priority at 7 interrupt vector at 42 MOVEW 0742 DMAINT1 AO Initialize channel status reg Clear the DONE BES BED CONF and BRKP bits to allow...

Page 293: ...ule Base Address Reg EOU FFFFFOOO SIM40 MBAR address value DMA Channel 1 equates DMACH1 EOU 780 DMAMCR1 EOU 0 Offset from MBAR for channel 1 regs MCR for channel 1 Channel 1 register offsets from channel 1 base address DMAINT1 EOU 4 interrupt register channel 1 DMACCR1 EOU 8 control register channel 1 DMACSR1 EOU A status register channel 1 DMAFCR1 EOU B function code register channel 1 DMASAR1 EO...

Page 294: ...ace for source and destination MOVE B DD DMAFCR1 AO Initialize source operand address Source address is equal to 6000 MOVE L SARADD DMASAR1 AO Initialize destination operand address Destination address is equal to 8000 MOVE L DARADD DMADAR1 AO Initialize the byte transfer count reg The number of bytes to be transferred is E or 7 words MOVE L NUMBYTE DMABTC1 AO Channel control reg init and Start DM...

Page 295: ...unction code register channel 1 DMASAR1 EQU C source address register channel 1 DMADAR1 EQU 10 destination address register channel 1 OMABTC1 EQU 14 byte transfer count register channel 1 SARADD EQU 6000 source address DARADD EQU 8000 destination address NUMBYTE EQU 64 number of bytes to transfer Initialize DMA Channel 1 LEA MODBASE DMACH1 AO Pointer to channel 1 Initialize DMA channel 1 MCR Norma...

Page 296: ...estination write cycle Source address is not incremented Increment the destination address Source size is word destination size is word REO is internal 100 of bus bandwidth dual address transfers start the DMA transfers MOVE W 068D DMACCR1 AO END Example 4 Cycle Steal Request Generation Dual Address Transfers MC68340 basic DMA channel register initialization example code This code is used to initi...

Page 297: ...fer Initialize DMA Channel 1 LEA MODBASE DMACH1 AO Pointer to channel 1 Initialize DMA channel 1 MCR Normal Operation ignore FREEZE dual address mode ISM field at O Make CPU32 SR 12 10 bits are less than or equal to ISM bits for channel startup Supervisor user reg unrestricted MAID field at 4 IARB priority at 8 MOVEW OOC8 AO Clear channel control reg Clear STR start bit to prevent the channel from...

Page 298: ...r count register The number of bytes to be transferred is 14 or 20 bytes MOVE L NUMBYTE DMABTC1 AO Channel control reg init and Start DMA transfers No interrupts are enabled source read cycle Increment the source and destination addresses Source size is byte destination size is word REO is external cycle steal dual address transfers start the DMA transfers MOVE W 1 DB1 DMACCR1 AO END MOTOROLA MC68...

Page 299: ...MC68340 USER S MANUAL MOTOROLA ...

Page 300: ...sists of the following major functional areas Two Independent Serial Communication Channels A and B Baud Rate Generator Logic Internal Channel Control Logic Interrupt Control Logic SERiAl COMMUNICATIONS CHANNELS AAND B BAUD RATE GENERATOR LOGIC INTERNAL CHANNEL CONTROL LOGIC INTERRUPT CONTROL LOGIC CTSA RTSA RxDA TxDA RxRDYA TxRDYA CTSB RTSB RxDB TxDB A X2 SCLI Figure 7 1 Simplified Block Diagram ...

Page 301: ... 8k Baud External 1x Clock or 16x Clock Programmable Data Format Five to Eight Data Bits Plus Parity Odd Even No Parity or Force Parity Nine Sixteenths to Two Stop Bits Programmable in One Sixteenth Bit Increments Programmable Channel Modes Normal Full Duplex Automatic Echo Local Loopback Remote Loopback Automatic Wakeup Mode for Multidrop Applications Seven Maskable Interrupt Conditions Parity Fr...

Page 302: ...nerator operates from the oscillator or external TTL clock input and is capable of generating 19 commonly used data communication baud rates ranging from 50 to 76 8k by producing internal clock outputs at 16 times the actual baud rate Refer to 7 2 Serial Module Signal Definitions and 7 3 1 Baud Rate Generator for additional information The external clock input SCLK which bypasses the baud rate gen...

Page 303: ...gisters Only certain output port pins are available There are no IP pins on the MC68340 RxRTS and TxRTS are more automated on the MC68340 The XTAL_RDY bit in the ISR should be polled until it is cleared to prevent an unstable frequency from being applied to the baud rate generator The following code is an example if XTAL_RDY O begin write CSR end else begin wait jump loop end 7 2 SERIAL MODULE SIG...

Page 304: ... external clock signal at 3 6864 MHz must be supplied when using the baud rate generator If a crystal is used a capacitor of approximately 10 pF should be connected from this signal to ground If this input is not used it must be connected to VCC or GND Refer to Section 10 Applications for an example of a clock driver circuit 7 2 2 Crystal Output X2 This output is the additional connection to a cry...

Page 305: ...signal is the transmitter serial data output for channel B The output is held high mark condition when the transmitter is disabled idle or operating in the localloopback mode Data is shifted out on this signal at the falling edge of the clock source with the least significant bit transmitted first 7 2 7 Channel B Receiver Serial Data Input RxDB This signal is the receiver serial data input for cha...

Page 306: ...status register SRA This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character 7 2 12 2 OP6 When used for this function this output is controlled by bit 6 in the OP 7 2 13 Channel A Receiver Ready RxRDYA This active low output signal is programmable as the channel A receiver ready channel A FIFO full indicator or a dedicate...

Page 307: ... used as a divide by 1 clock and an asynchronous clock mode when used as a divide by 16 clock The clock is selected by programming the clock select register CSR for each channel BAUD RATE GENERATOR LOGIC CRYSTAL OSCILLATOR EXTERNAL INTERFACE X1 BAUD RATE X2 GENERATOR SCLK t CLOCK SELECTORS Figure 7 3_ Baud Rate Generator Block Diagram 7 3 2 Transmitter and Receiver Operating Modes The functional b...

Page 308: ...ER HOLDING REGISTER 2 RECEIVER HOLDING REGISTER 3 BUFFER RBA I RECEIVER SHIFT REGISTER 4 REGISTERS L r __R_E_C_EI_VE_R_HO_LD_IN_G_R_EG_IS_T_ER_1____ R x FIFO EXTERNAL INTERFACE TxDA RxDA RECEIVER HOLDING REGISTER 2 1 RECEIVER HOLDING REGISTER 3 RxDB RECEIVE _________ ______ l __ BUFFER RBB RECEIVER SHIFT REGISTER 4 REGISTERS NOTE RfN READ wRITE R READ W WRITE Figure 7 4 Transmitter and Receiver Fu...

Page 309: ...ta is shifted from the transmitter output on the falling edge of the clock source TxDx TRANSMiTIER ENABLED TxRDY SR2 C11N TRANSMISSION RTS2 MANUAlLY ASSERTED nMANUAlLY I B_Y_M_ _SE_TOO __ M_WW_D ______________________________ RTED NOTES 1 TIMING SHOWN FOR MR2 4 1 2 TIMING SHOWN FOR MR2 S l 3 CN a TRANSMIT CHARACTER 4 W WRlTE Figure 7 5 Transmitter Timing Diagram Following transmission of the stop ...

Page 310: ...clock for eight clocks starting one half clock after the transition asynchronous operation or at the next rising edge of the bit time clock synchronous operation If RxDx is sampled high the _ start bit is invalid and the search for the valid start bit begins again If RxDx is still low a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theor...

Page 311: ...acter in the receiver first in first out FIFO stack and sets the corresponding error conditions and RxRDY bit in the SA Then if the break perSists until the next character time the receiver places an all zero character into the receiver FIFO and sets the corresponding RS and RxRDY bits in the SA 7 3 2 3 FIFO STACK The FIFO stack is used in each channel s receiver buffer logic The stack consists of...

Page 312: ...tion speed advantage but does have a disadvantage since each character is not individually checked for error conditions by software If an error occurs within the message the error is not recognized until the final check is performed and no indication exists as to which character in the message is at fault In either mode reading the SR does not affect the FIFO The FIFO is popped only when the recei...

Page 313: ...are transmitted as received A received break is echoed as received until the next valid start bit is detected 7 3 3 2 LOCAL LOOPBACK MODE In this mode TxDx is internally connected to RxDx This mode is useful for testing the operation of a local serial module channel by sending data to the transmitter and checking data assembled by the receiver In this manner correct channel operations can be assur...

Page 314: ...e of the slave stations The slave stations have their channel receivers disabled However they continuously monitor the data stream sent out by the master station When an address character is sent by the master the slave receiver channel notifies its respective CPU by setting the RxRDY bit in the SR and generating an interrupt if programmed to do so Each slave station CPU then compares the received...

Page 315: ...data NO bit flag and a programmed number of stop bits The NO bit identifies the type of character being transmitted to the slave station The character is interpreted as an address character if the NO bit is set or as a data character if the NO bit is cleared The polarity of the NO bit is selected by programming bit 2 of the MR1 The MR1 should be programmed before enabling the transmitter and loadi...

Page 316: ... the CPU32 with no wait states The serial module responds to byte reads Reserved registers return logic zero during reads 7 3 5 2 WRITE CYCLES The serial module is accessed by the CPU32 with no wait states The serial module responds to byte writes Write cycles to read only registers and reserved registers complete in a normal manner without exception processing however the data is ignored 7 3 5 3 ...

Page 317: ...rom the base address specified in the module base address register MBAR in the SIM40 The numbers above the register description represent the bit position in the register The register description contains the mnemonic for the bit The values shown below the register description are the values of those register bits after a hardware reset A value of U indicates that the bit value is unaffected by re...

Page 318: ...ER B TBB 71C SIU DO NOT ACCEss3 DO NOT ACCEss3 710 SIU INPUT PORT REGISTER IP OUTPUT PORT CONTROL REGISTER OPCR 71E SJU DO NOT ACCEss3 OUTPUT PORT OP 4 lIT SET 71F SIU DO NOT ACCEss3 OUTPUT PORT OP 4 BIT RESET 720 SIU MODE REGISTER 2A MR2A MODE REGISTER 2A MR2A 721 SJU MODE REGISTER 2B MR2B MODE REGISTER 2B MR2B NOTES 1 S Register permanently defined as supervisor only access 2 SIU Register progra...

Page 319: ...xecuting the LPSTOP instruction to obtain the lowest power consumption The X1 X2 oscillator will continue to run during LPSTOP if STP O FRZ1 FRZo Freeze These bits determine the action taken when the FREEZE signal is asserted on the 1MB when the CPU32 has entered background debug mode Table 7 1 lists the action taken for each combination of bits Table 7 1 FRZx Control Bits FRZ1 FRZO Action 0 0 Ign...

Page 320: ...e IARB field to a value from F highest priority to 1 lowest priority 7 4 1 2 INTERRUPT LEVEL REGISTER ILR The ILR contains the priority level for the serial module interrupt request When the serial module is enabled Le the STP bit in the MCR is cleared this register can be read or written to at any time while in supervisor mode ILR 704 7 6 5 4 3 2 0 I 0 I 0 I 0 I 0 I 0 112 IL1 I ILO I RESET 0 0 0 ...

Page 321: ...is negated if the channel s FIFO is full RTSx is reasserted when the FIFO has an empty position available o RTSx is asserted by setting bit 1 or 0 in the OP and negated by clearing bit 1 or 0 in the OP This feature can be used for flow control to prevent overrun in the receiver by using the RTSx output to control the CTSx input of the transmitting device If both the receiver and transmitter are pr...

Page 322: ...rforms a parity check on incoming data These bits can alternatively select multidrop mode for the channel PT Parity Type This bit selects the parity type if parity is programmed by the parity mode bits and if multidrop mode is selected it configures the transmitter for data character transmission or address character transmission Table 7 2 lists the parity mode and type or the multidrop mode for e...

Page 323: ...alf bit time which is equal to two successive edges of the internal or external 1x clock or 16 successive edges of the external 16x clock The received break circuit detects breaks that originate in the middle of a received character However if a break begins in the middle of a character it must persist until the end of the next detected character time o No break has been received FE Framing Error ...

Page 324: ...hannel B 1 The transmitter holding register is empty and ready to be loaded with a character This bit is set when the character is transferred to the transmitter shift register This bit is also set when the transmitter is first enabled Characters loaded into 7 the transmitter holding register while the transmitter is disabled are not transmitted and are lost o The transmitter holding register was ...

Page 325: ...r the channel receiver from a set of baud rates listed in Table 7 4 The baud rate set selected depends upon the auxiliary control register ACR bit 7 Set 1 is selected if ACR bit 7 0 and set 2 is selected if ACR bit 7 1 The receiver clock is always 16 times the baud rate shown in this list except when SCLK is used Table 7 4 RCSx Control Bits RCS3 RCS2 RCS1 RCSO Set 1 Set 2 0 0 0 0 50 75 0 0 0 1 110...

Page 326: ... 1200 1200 0 1 1 1 1050 2000 1 0 0 0 2400 2400 1 0 0 1 4BOO 4Boo 1 0 1 0 7200 1BOO 1 0 1 1 9600 9600 1 1 0 0 3B 4k 19 2k 1 1 0 1 76 Bk 3B 4k 1 1 1 0 SCLKl16 SCLKl16 1 1 1 1 SCLKl1 SCLKl1 7 4 1 7 COMMAND REGISTER CR The CR is used to supply commands to the channel Multiple commands can be specified in a single write to the CR if the commands are not conflicting e g reset transmitter and enable tran...

Page 327: ...gisters are unaltered This command should be used in lieu of the receiver disable command whenever the receiver configuration is changed because it places the receiver in a known state Reset Transmitter The reset transmitter command resets the channel transmitter The transmitter is immediately disabled and the TxEMP and TxRDY bits in the SR are cleared All other registers are unaltered This comman...

Page 328: ...Sx output high TC1 TC Transmitter Commands These bits select a single command as listed in Table 7 7 Table 7 7 TCx Control Bits TC1 TCO Command 0 0 No Action Taken 0 1 Enable Transmitter 1 0 Disable Transmitter 1 1 Do Not Use No Action Taken The no action taken command causes the transmitter to stay in its current mode If the transmitter is enabled it remains enabled if disabled it remains disable...

Page 329: ...mmand has no effect Do Not Use Do not use this bit combination because the result is indeterminate 7 4 1 8 RECEIVER BUFFER RB The receiver buffer contains three receiver holding registers and a serial shift register The channel s RxDx pin is connected to the serial shift register The holding registers act as a FIFO The CPU32 reads from the top of the stack while the receiver shifts and updates fro...

Page 330: ...6 5 4 3 2 1 0 1 0 1 0 ICOSBICOSAI 0 10 ICTSBlcTSAI RESET o o Read Only Bits 7 6 3 2 Reserved COSe COSA Chanoe of State o o o o u u Supervisor User 1 A change of state high to Iow or low to high transition lasting longer than 25 50 J 1S when using a crystal as the sampling clock or longer than one or two periods when using SCLK has occurred at the corresponding CTSx input MCR ICCS bit controls sele...

Page 331: ...to enable interrupts 0 Setting the corresponding bit in the IPCR has no effect on ISR bit 7 7 4 1 12 INTERRUPT STATUS REGISTER ISR The ISR provides status for all potential interrupt sources The contents of this register are masked by the lEA If a flag in the ISR is set and the corresponding bit in IER is also set the IRQx output is asserted If the corresponding bit in the IER is cleared the state...

Page 332: ... FIFO is full the bit will be set again when the waiting character is loaded into the FIFO TxRDYB Channel B Transmitter Ready This bit is the duplication of the TxRDY bit in SRB 1 The transmitter holding register is empty and ready to be loaded with a character This bit is set when the character is transferred to the transmitter shift register This bit is also set when the transmitter is first ena...

Page 333: ...cter This bit is set when the character is transferred to the transmitter shift register This bit is also set when the transmitter is first enabled Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted o The transmitter holding register was loaded by the CPU32 or the transmitter is disabled 7 4 1 13 INTERRUPT ENABLE REGISTER IER The IER selec...

Page 334: ...s the current state of the CTSx inputs This register can only be read when the serial module is enabled Le the STP bit in the MCR is cleared IP 710 7 6 I n I n RESET o o Read Only CTSB CTSA Current State 5 4 I n I n o o 3 2 1 0 I n I n I r T R I r T A I o o u u Supervisor User 1 The current state of the respective CTSx input is negated o The current state of the respective CTSx input is asserted T...

Page 335: ...P6ITxRDYA pin functions as a dedicated output The signal reflects the complement of the value of bit 6 of the OP OP4 0utput Port 4 RxRDYA 1 The OP4 RxRDYA pin functions as the FIFO full or receiver ready signal for channel A depending on the value of bit 6 of MR1 A The signal reflects the complement of the value of ISR bit 1 thus RxRDYA is a logic zero when the receiver is ready 0 The OP4 RxRDYA p...

Page 336: ...TP bit in the MCR is cleared Bit Set OP 71E 7 6 5 4 3 2 1 0 IOP7 IOPS I 5 IOP4 IOP3 IOP2 10Pf Iopo I RESET 0 0 0 0 0 0 0 0 Write Only Supervisor User NOTE OP bits 7 5 3 and 2 are not pinned out on the MC68340 thus changing these bits has no effect OP6 OP4 OP1 OPO Output Port Parallel Outputs i _ Thnron hi _ h __ ___ _ ___ __ 1_ _ _ _ J _ _ Oo r _ _ o These bits are not affected by writing a zero t...

Page 337: ...ion of the RTSA or RTSB signals The output is normally asserted by setting OPO or OP1 and negated by clearing OPO or OP1 see 7 4 1 15 Output Port Control Register OPCR 7 38 1 In applications where the transmitter is disabled after transmission is complete setting this bit causes the particular OP bit to be cleared automatically one bit time after the characters if any in the channel transmit shift...

Page 338: ...sixteenth bit are programmable for character lengths of six seven and eight bits For a character length of five bits one and one sixteenth to two bits are programmable in increments of one sixteenth bit In all cases the receiver only checks for a high condition at the center of the first stop bit position i e one bit time after the last data bit or after the parity bit if parity is enabled If an e...

Page 339: ... When called SINIT places the specified channel in the local loopback mode and checks for the following errors Transmitter Never Ready Receiver Never Ready Parity Error Incorrect Character Received 7 4 2 2 1 0 DRIVER EXAMPLE The 1 0 driver routines consist of INCH OUTCH and POUTCH INCH is the terminal input character routine and gets a character from the channel A receiver and places it in the low...

Page 340: ...MOTOROLA INnA1E CHANNEL A CHANNELB INTERRUPTS ENABlA Figure 7 10 Serial Module Programming Flowchart 1 of 5 MC68340 USER S MANUAL 7 41 ...

Page 341: ...LOCAL LOOPBACK MODE ENABLE CHANNEL S TRANSMITIER CLEAR CHANNEL STATUS WORD SET TRANSMITTER NEVER READY FLAG SET RECEIVER NEVER READY FLAG Figure 7 10 Serial Module Programming Flowchart 2 of 5 MC68340 USER S MANUAL MOTOROLA ...

Page 342: ... Figure 7 10 Serial Module Programming Flowchart 3 of 5 MOTOROLA MC68340 USER S MANUAL 7 43 ...

Page 343: ...44 REMOVE BREAK CHARACTER FROM RECEIVER AFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS INCH Figure 7 10 Serial Module Programming Flowchart 4 of 5 MC68340 USER S MANUAL MOTOROLA ...

Page 344: ...NDAUNE FEED CHARACTER TO CHANNEL A TRANSMITTER OUTCHR RETURN N N POUCH SEND CHARACTER IN DO TO CHANNEL BTRANSMITTER SEND AUNE FEED CHARACTER TO CHANNELB TRANSMITTER POUTCHR RETURN N N Figure 7 10 Serial Module Programming Flowchart 5 of 5 MC68340 USER S MANUAL 7 45 ...

Page 345: ... Select the input capture clock ICCS bit Select the access privilege for the supervisor user registers SUPV bit Select the interrupt arbitration level for the serial module IARBx bits Interrupt Vector Register IVR Program the vector number for a serial module interrupt Interrupt Level Register ILR Program the interrupt priority level for a serial module interrupt Interrupt Enable Register IER Enab...

Page 346: ... SBx bits Command Register CR Enable the receiver and transmitter 7 5 2 Serial Module Example Configuration Code The following code is an example of a configuration sequence for the serial module MvOO J4U DaSle senal moaUie register initialization example coae This code is used to initialize the 68340 s internal serial module registers providing basic functions for operation It sets up serial chan...

Page 347: ...operation ignore FREEZE select the crystal clock Supervisor user serial registers unrestricted Interrupt arbitration at priority 02 MOVE B 00 MCRH AO MOVE B 02 MCRL AO WAIT FOR TRANSMITTER EMPTY OR TIMEOUT MOVE W 2000 DO init loop counter XBMTWAIT EOU BTST 3 SRA AO TX empty in status reg NOP DBNE DO XBMTWAIT loop until set or timeout NEGATE RTSA SIGNAL OUTPUT MOVE B O OPCR AO MOVE B 01 OP_BR AO RE...

Page 348: ... SET UP BAUD RATE FOR PORT IN CLOCK SELECT REGISTER MOVE B BB CSRA AO Set 9600 baud for RX and TX SET RTSA ACTIVE MOVE B 01 OP_BS AO set RTSA OPO output ENABLE PORT MOVE B 45 CRA AO Reset error status enable RX TX END MOTOROLA MC68340 USER S MANUAL 7 49 ...

Page 349: ...7 50 MC68340USER S MANUAL MOTOROLA ...

Page 350: ... romf TIMER 2 TOUT2 1TGATE2 INTERRUPT INTERRUPT CONTROL CONTROL LOGIC LOGIC 1MB INTERFACE 8 INTERFACE Figure 8 1 Simplified Block Diagram 8 1 MODULE OVERVIEW Each timer module consists of the following functional features Versatile General Purpose Timer 8 Bit Prescaler 16 Bit Counter Timers Can Be Externally Cascaded for a Maximum Count Width of 48 Bits Programmable Timer Modes Input Capture Outpu...

Page 351: ... to FF and the counter is set to 0000 The counter is loaded with a programmed value on the first falling edge of the counter clock after the timer is enabled and again when a timeout occurs counter reaches 0000 The prescaler and counter can be used as one 24 bit counter by enabling the prescaler and selecting the divide by 256 prescaler output Refer to 8 4 Register Description for additional infor...

Page 352: ...ock CLKOUT This output of the first multiplexer called selected clock is applied to both the 8 bit prescaler and the second multiplexer The second multiplexer selects the clock for the 16 bit counter which is either the selected clock or the 8 bit prescaleroutput 8 1 2 Internal Control Logic The timer receives operation commands on the 1MB and in turn issues appropriate operation signals to the in...

Page 353: ...events that may cause an interrupt 8 2 TIMER MODULES SIGNAL DEFINITIONS This section contains a brief description of the timer module signals see Figure 8 3 8 4 NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent ...

Page 354: ...8 2 1 Timer Input TIN1 TIN2 This input can be programmed to be the clock that causes events to occur in the counter and prescaler TINx is internally synchronized to the system clock to guarantee that a valid TINx level is recognized Additionally the high and low levels of TINx must each be stable MOTOROLA MC68340 USER S MANUAL 8 5 ...

Page 355: ...uce unpredictable results 8 3 1 Input Capture Output Compare This mode has the capability of capturing a counter value by holding the value in the counter register CNTR Additionally this mode can provide compare information via TOUTx to indicate when the counter has reached the compare value This mode can be used for square wave generation pUlse width modulation or periodic interrupt generation Th...

Page 356: ...ardless of the value of TGATEx When the counter counts down to the value contamea m me l UM tniS conoltlon IS reflected by setting the timer compare TC and compare COM bits in the SR TOUTx responds as selected by the OCx bits in the CR The output level OUT bit in the SR reflects the value on TOUTx Shadowing does not affect this operation If the counter counts down to 0000 a timeout is detected cau...

Page 357: ... loaded with the value stored in the PREL1 N With each successive falling edge of the counter clock the counter decrements The time between enabling the timer and the first timeout can range from N to N 1 periods When TGATEx is used to enable the timer the enabling of the timer is asynchronous however if timing is carefully considered the time to the first timeout can be known For additional detai...

Page 358: ...square wave with virtually any duty cycle The square wave is generated by counting down from the value in the PREL1 to timeout count value 0000 then loading that value from PREL2 and again counting down to timeout When this second timeout occurs the value from P I I 1 ic IO lrlArl intn thA counter and the cvcle reDeats TOUTx can be programmed to change state with every timeout thus generating a va...

Page 359: ...er is re enabled and begins counting from the value attained when TGATEx was negated The ON bit is set again If TGATEx is not enabled TGE 0 TGATEx has no effect on the operation of the timer In this case the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set The SR TG bit cannot be set At all times the TGL bit in the SR re...

Page 360: ... held high disabling the prescaler and counter Additionally the SR ON and COM bits are cleared TOUTx behaves as a variable width pulse when the OCx bits of the CR are programmed for toggle mode TOUTx is a logic zero between the time that the timer is enabled and the first timeout When this event occurs TOUTx transitions to a logic one The second timeout occurs after N2 1 periods allowing for the z...

Page 361: ...etting the SWR CPE and TGE bits in the CR Asserting TGATEx starts the counter When the timer is enabled the SR ON bit is set On the next falling edge of the counter clock the counter is loaded with the value FFFF With each successive falling edge of the counter clock the counter decrements The PREL1 and PREL2 registers are not used in this mode When TGATEx is negated the SR TG bit is set the ON bi...

Page 362: ... counting down from FFFF The negation of TGATEx has no effect on the counter When TGATEx is reasserted the counter stops counting and holds the value at which it stopped Further assertions and negations of TGATEx have no effect on the counter This mode can be selected by programming the CR MODEx bits to 101 The timer is enabled by setting the SWR CPE and the TGE bits in the CR The assertion of TGA...

Page 363: ...in the CNTR must be read inverted and incremented by 1 the first count is FFFF which in effect includes a count of zero The counter counts in a true 216 fashion For measuring pulses of even greater duration the value in the pax bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR NOTE Once the timer has been enabled do not clear the SR TG bit ...

Page 364: ...n of TGATEx starts the counter The negation of TGATEx disables the counter sets the SR TG bit and clears the ON bit in the SA If TGATEx is reasserted the timer resumes counting from where it was LUjJjJt U dliU lilt VI ll un I tn ctgctm runner assemons ana negallons OJ 11 11 1eX nave the same effect The TGL bit in the SR reflects the level of TGATEx at all times If the counter counts down to the va...

Page 365: ...in the SR reflects the level of TGATEx TGATEx can also be used as an input port that generates interrupts on a low to high transition of TGATEx when the CR is configured as follows CR TGATEx AS AN INPUT INTERRUPT x x x x x x x x x x When TGATEx is negated the SR TG bit is set and the programmed IRQx signal is asserted to the CPU32 The TG bit can only be cleared by writing a one to this bit positio...

Page 366: ...The timer is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration The vector number must be provided if interrupt servicing is necessary thus the interrupt register IR must be initialized If the IR is not initialized a spurious interrupt _ _ exception Will De taKen IT Interrupt servicing IS necessary 8 4 REGISTER DESCRIPTION The...

Page 367: ...s the offset for timer 2 The numbers on the top line of the register represent the bit position in the register The register contains the mnemonic for the bit The value of these bits after a hardware reset is shown below the register The access privilege is shown in the lower right hand corner NOTE A CPU32 RESET instruction will not affect the MCR but will reset all other registers in the timer mo...

Page 368: ......

Page 369: ...et from the base of the vector table where the address of the exception handler for the specified interrupt is located The IV field is reset to OF which indicates an uninitialized interrupt condition See Section 5 CPU32 for more information 8 4 3 Control Register CR The CR controls the operation of the timer The register can always be read or written when the timer module is enabled i e the STP bi...

Page 370: ...t on the timer operation PCLK Prescaler Clock Select This bit selects which clock is used for the counter clock 1 The counter is decremented by the prescaler output tap as selected by the POT field in the CR o The counter is decremented by the selected clock I ne prescaler continues to aecrement regaraless aT now I GLK is set CPE Gounter Prescaler Enable 1 The selected clock is enabled If the TGE ...

Page 371: ...ing Modes for more information on the individual modes Table 8 5 MODEx Encoding MODE2 MODE1 MODEO OPERATION MODE 0 0 0 Input Capture Output Compare 0 0 1 Square Wave Generator 0 1 0 Variable Duty Cycle Square Wave Generator 0 1 1 Variable Width Single Shot Pulse Generator 1 0 0 Pulse Width Measurement 1 0 1 Period Measurement 1 1 0 Event Count 1 1 1 Timer Bypass Simple Test Mode OC1 QCO Output Con...

Page 372: ...ompare mode TOUTx is immediately set to one if the timer is disabled SWR 0 If the timer is enabled SWR 1 TOUTx will be set to one at timeouts and set to zero at timer compare events If the COM is 0000 TOUTx will be set to one at the timeout timer compare event 8 4 4 Status Register SR The SR contains timer status information as well as the state of the prescaler This register is updated on the ris...

Page 373: ...imer SWR 0 TC Timer Compare Interrupt 1 This bit is set when the counter transitions off a clock event falling edge to the value in the COM This bit does not affect the programmed IRQx signal if the lEO bit in the CR is cleared a This bit is cleared by the timer whenever the RESET signal is asserted on the 1MB regardless of the mode of operation This bit may also be cleared by writing a one to it ...

Page 374: ...k except in the input capture output compare mode when a read of the register is not in progress This read only register can be read when the timer module is enabled Le the STP bit in the MCR is cleared CNTR 15 RESET o 14 o 13 12 o o 11 10 9 8 o o o o 60A 64A 7 6 5 4 3 2 o o o o o o o o o Supervisor User 1 All 24 DItS Of me prescaler ana me counter may De ODlaineO oy one long wofu ftli lU i ll lIl...

Page 375: ...d However a write to this register must be completed before timeout for the new value to be reliably loaded into the counter PREL2 60E 64E 15 14 13 12 11 10 8 7 6 5 4 3 2 o RESET Supervisor User 8 4 8 Compare Register COM The COM can be used in any mode When the 16 bit counter reaches the value in the COM the TC and COM bits in the SR are set In the input capture output compare mode a compare even...

Page 376: ...r the TO TG and TG bits to reset the interrupts Module Configuration Register MCR Initialize the STP for normal operation Select whether to respond to or ignore FREEZE FRZx bits Select the access privilege for the supervisor user registers SUPV bit Select the interrupt arbitration level for the timer module IARBx bits 1_ __ C_ _r 110 _ w _ _ 0 1 Program the interrupt priority level for the timer i...

Page 377: ...It sets up timer1 for square wave generation equates MBAR MODBASE EQU 0003FFOO Address of SIM40 Module Base Address Reg EQU FFFFFOOO SIM40 MBAR address value Timer1 module equates TIMER1 EQU 600 MCR1 EQU 0 Offset from MBAR for timer1 module regs MCR for timer1 Timer1 register offsets from timer1 base address IR1 EQU 604 interrupt register timer1 CR1 EQU 606 control register timer1 SR1 EQU 608 stat...

Page 378: ...ected clock is 1 2 system s freq Square wave generation toggle TOUT MOVE W 8205 CR1 AO END r Jl R lln h il timpr mnrh riP rAni tAr initi l1i7 ltion 8x Imole code This code is used to initialize the 68340 s internal timer module registers providing basic functions for operation It sets up timer1 for pulse width measurement In this mode the number of clock cycles during a particular event are counte...

Page 379: ... LOOP2 BTST B 3 SR1 AO BEQ B LOOP2 Ready to initialize timer1 TGATE is negated Module configuration register Timer1 module is set for normal operation ignore FREEZE Supervisor user timer1 registers unrestricted Interrupt arbitration at priority 03 MOVE W 0003 MCR1 AO Initialize timer1 interrupt level to 2 and vector to OF MOVE W 020F IR1 AO Initialize the compare register to 0 CLR W COM1 AO Clear ...

Page 380: ...When TG 1 counting is stopped LOOP3 BTST B 5 SR1 AO BEQ B LOOP3 Counting is complete To determine the number of cycles counted the value in CNTR1 must be read inverted and incremented by 1 MOVE W CNTR1 AO DO NOT W DO ADDQ W 1 00 DO contains the number of cycles counted END MOTOROLA MC68340 USER S MANUAL 8 31 ...

Page 381: ...8 32 MC68340 USER S MANUAL MOTOROLA ...

Page 382: ...ent of the device system logic The MC68340 implementation provides the following capabilities a Perform boundary scan operations to test circuit board electrical continuity b Sample the MC68340 system pins during operation and transparently shift out the result in the boundary scan register c Bypass the MC68340 for a given circuit board test by effectively reducing the boundary scan register to a ...

Page 383: ...r that is sampled on the rising edge of TCK TOO a three state test data output that is actively driven in the shift IR and shift DR controller states TOO changes on the falling edge of TCK TEST DATA REGISTERS TCK f TAP M U x CT ________________________________ Figure 9 1 Test Access Port Block Diagram 9 2 TAP CONTROLLER TOO The TAP controller is responsible for interpreting the sequence of logical...

Page 384: ...xcept the open drain 1 0 pins DONE1 DONE2 HALT and RESET have a single register bit for pin data and an associated control bit in the boundary scan register All open drain 1 0 pins have two register bits input and output for pin data and no associated control bit To ensure proper operation the open drain pins require external pullups Twenty three control bits in the boundary scan register define t...

Page 385: ...ontrol bit For example the active high level for irq7 ctl bit 52 is logic zero since the cell type is 10 CtI0 The active level for ab ctl bit 83 is logic one since the cell type is 10 CtI1 10 Ct10 see Figure 9 6 differs from 10 Ct11 see Figure 9 5 by an inverter in the output enable path The fourth column lists the pin type TS Output indicates a three state output pin 1 0 indicates a bidirectional...

Page 386: ...0 Cell A13 I O ab ctl 49 O Latch DONE2 00 1 0 15 10 Cell A12 I O ab ctl 50 I Pin OONE2 00 110 16 10 Cell All I O ab ctl 51 IO CeU IRQ7 110 irq7 ctl 17 10 CeIl Al0 I O ab ctl 52 10 Ct10 irq7 ctl 18 10 Cell A9 I O ab ctl 53 10 Cell IR06 I O irq6 ctl 19 10 Cell A8 I O ab ctl 54 IO CtIO irq6 ctl lI 11 11 A 7 I n I _II __ d _ __ 21 10 Cell A6 I O ab ctl 56 10 Ct10 irq5 ctl 22 10 Cell AS I O ab ctl 23 1...

Page 387: ...118 I Pin RESET 88 10 Cell A25 I O ab25 ell 119 O Latch CLKOUT 89 IO CtIO ab25 ell 120 I Pin EXTAL 90 10 CeIl A26 I O ab26 ell 121 10 Cell MOOCK 91 IO CtIO ab26 ell 122 10 Ct10 modck ell 92 IO Cell A27 I O ab27 ell 123 O Latch IPIPE 93 IO CtIO ab27 ell 124 10 Cell IFETCH 94 IO Cell A28 I O ab28 ell 125 10 Ct10 ifetch ell 95 IO CtIO ab28 ell 126 I Pin BKPT 96 10 Cell A29 I O ab29 ell 127 O Latch FR...

Page 388: ...__ ______ TO OUTPUT BUFFER DATA TO SYSTEM LOGIC MOTOROLA FROM LAST CELL MUX CLOCK DR UPDATE DR Figure 9 3 Output Latch Cell O Latch 1 EXTEST TO NEXT 0 OTHERWISE CELL dt lr 10 L I 10 C1 UPDATE DR CLOCK DR FROM LAST SHIFT DR CELL Figure 9 4 Input Pin Cell Pln MC68340 USER S MANUAL 9 7 ...

Page 389: ...ST CEll t f10 f C1 R CLOCK DR RESET UPDATE DR Figure 9 5 Active High Output Control Cell IO CtI1 1 EXTEST 0 OTHERWISE TO NEXT CEll CONT ___F l FROM TO OUTPUT ENABlE 1 0RIVE SYSTEM MUX t i LOGIC SHIFT DR FROM LAST CEll f C1 R CLOCK DR RESET UPDATE DR Figure 9 6 Active Low Output Control Cell IO CtIO MC68340 USER S MANUAL MOTOROLA ...

Page 390: ...E More than one IO Cel could be serially connected and conb olled by a single IO ClIx cell Figure 9 8 General Arrangement for Bidirectional Pins 9 4 INSTRUCTION REGISTER The MC68340 IEEE 1149 1 implementation includes the three mandatory public instructions EXTEST SAMPLE PRELOAD and BYPASS but does not support any of the optional public instructions defined by IEEE 1149 1 One additional public ins...

Page 391: ...rystal clock source The LOC bit is clear when a clock is detected and set when it is not The lOC bit is always clear when an external clock is used The lOC bit can be used to detect faulty connectivity when a crystal is used to clock the device 9 4 1 EXTEST 000 The external test EXTEST instruction selects the 132 bit boundary scan register EXTEST asserts internal reset for the MC68340 system logic...

Page 392: ...eaister is selected by the current instruction the shift reaister staae is set to a logic zero on the rising edge of TCK in the capture DR controller state Therefore the first bit to be shifted out after selecting the bypass register will always be a logic zero 9 4 4 HI Z 100 The HI Z instruction is not included in the IEEE 1149 1 standard It is provided as a manufacturer s optional public instruc...

Page 393: ... TCK input is not blocked in LPSTOP mode To consume minimal power the TCK input should be externally connected to VCC or ground 3 The TMS and TDI pins include on chip pullup resistors In LPSTOP mode these two pins should remain either unconnected or connected to Vcc to achieve minimal power consumption 9 6 NON IEEE 1149 1 OPERATION In non IEEE 1149 1 operation there are two constraints First the T...

Page 394: ...ial Interface CLOCK IQr IIITClV SERiAl INTERFACE bd bd SRAM I I MC68340 ROM Figure 10 1 Minimum System Configuration Block Diagram 10 1 1 Processor Clock Circuitry The MC68340 has an on chip clock synthesizer that can operate from an on chip phase locked loop PLL and a voltage controlled oscillator VCO The clock synthesizer uses an external crystal connected between the EXTAL and XTAL pins as a re...

Page 395: ...lock circuits The source for VCCSYN should be a quiet power supply and external bypass capacitors see Figure 10 4 should be placed as close as possible to the VCCSYN pin to ensure a stable operating frequency Additionally the PLL requires that an external low leakage filter capacitor typically in the range of 0 01 to 0 1 JlF be connected between the XFC and VCCSYN pins The XFC capacitor should pro...

Page 396: ...itry to decode address information and circuitry to return data and size acknowledge DSACKx is not required However external ICs are required to provide write enables for the high and low bytes of data Al5 A1 l ILU AD AS MC68340 rWi D15 DO MCM6206 35 rWi 1 CE Figure 10 5 SRAM Interface MCM62Q6 35 Riii CE D7 DO The SRAM interface shown in Figure 10 5 is a two clock interface at 16 78 MHz operating ...

Page 397: ...015 00 16 B1T ROM cso CE CE L Figure 10 6 ROM Interface 10 1 5 Serial Interface The necessary circuitry to create an RS 232 interface with the MC68340 includes an external crystal and an RS 232 receiver driver see Figure 10 7 The resistor and capacitor values shown are typical the crystal manufacturer s documentation should be consulted for specific recommendations on external component values The...

Page 398: ...n 8 bit D S7 A C Kx in two wait states see Figure 10 8 CLKOUT CP MR 393 ao 01 02 03 Figure 10 8 External Circuitry for 8 Bit Boot ROM The 393 is a falling edge triggered counter thus CSO is stable during the time in which it is being clocked CSO acts as the asynchronous reset i e when it is asserted the 393 is allowed to count The falling edge of S2 provides the first counting edge 01 does not tra...

Page 399: ...he second path is the time from CSx asserted to when data must be available to the processor Figure 10 10 Access Time Computation Diagram As shown in the diagram an equation for the address access time tADV can be developed as follows tADV tcydNc 0 5 ts9 ts27 where eyc system CLKOUT period Nc number of clocks per bus cycle ts6 CLKOUT high to address valid 30 ns maximum at 16 78 MHz ts27 data in va...

Page 400: ...ys through buffers or external logic that may be needed 10 2 3 Calculating Frequency Adjusted Output The general relationship between the CLKOUT and most input and output Signals is shown in Figure 10 11 Most outputs transition off of a falling edge of CLKOUT but the nrin inl annli t th tn t that tran t n nff nf a ri nn AnnA I _ _ CLKOUT __ I ______________ td r ____ OUTPUTS ASYNCHRONOUS T 7t K 7 ...

Page 401: ...ted tw is as follows tw tw N Tf 2 Tf 2 Tf 2 td where tw the frequency adjusted signal width tw the signal width at 16 78 MHz N the number of full one half clock periods in tw Tf 2 one half the new clock period Tf 2 one half the clock period at full speed td the propagation time from the clock edge The following calculation uses a 16 78 MHz part specification 14 AS width asserted at 12 5 MHz as an ...

Page 402: ...lf the new clock period Tf 2 one half the clock period at full speed td1 the propagation time for the first output from the clock edge The following calculation uses a 16 78 MHz port specification 21 RIW high to AS asserted at 8 MHz as an example 5 110 1IIIIIIIIIUIli N O T1 2 125 2 62 5 ns Tf 2 60 2 30 ns td1 30 ns maximum therefore ts 15 0 62 5 30 62 5 30 47 5 ns minimum In this manner new specif...

Page 403: ...yte accesses the data is transferred directly on 015 08 However during odd byte accesses the data must be routed on 015 08 for the 8 bit device and on 07 DO for the 16 bit memory 10 3 POWER CONSUMPTION CONSIDERATIONS The MC68340 can be designed into low power applications that involve high performance processing capability 32 bits high functional density small size portable capability and battery ...

Page 404: ...0 16 shows how voltage affects current drain at some typical operating temperatures Figure 10 17 shows how system clock frequency affects current drain 120 r Typical values 32KHz xtal 16 78 MHz 24 C 90 f 93 E i 60 30 o MOTOROLA 81 73 66 1 I III I I I I I 06 INITIALIZATION MAX CURRENT SERIAL OFF TIMER 1 OFF TIMER2 OFF DMA OFF ____ A_ _ __ _ __ _ I 1 lg 1 1 1 III MC68340 USER S MANUAL LPSTOP 10 11 ...

Page 405: ...e V 5 5 Figure 10 16 MC68340 Current vs VoltagelTemperature 120r 90 60 Typical values 32KHzxtal peak current 24 e 30 O ____ ____ L____ ________L ____ ____ ____ ________ ____ o 2 4 6 8 10 12 14 16 Clock Frequency MHz Figure 10 17 MC68340 Current vs Clock Frequency at 5 V MC68340 USER S MANUAL MOTOROLA ...

Page 406: ...Hz 95mA TBD Typical Current 8 MHz 55mA 30mA Standby Current 60 IlA 251lA Running at 3 3 V saves 66 of the power consumption The 3 3 V operati9n provides the following user advantages Advantage Benefit Lower Supply Voltage Fewer Batteries Fewer Batteries Less Weight Smaller Size Lower Current Drain Extended Battery Life Less Heat Generated No Fan _ _ _ Less EMF Radiation Easier FCC Certification Le...

Page 407: ...10 14 MC68340 USER S MANUAL MOTOROLA ...

Page 408: ...e 11 ___ l _L _ _ ____ b _______ 1 __ _ __ 1 l _ 1 1_ _1 _______ I ________ ___ _ _ 1 1 _ _a _ 11 _ _ __ _ 1 avoid exposure to voltages higher than maximum rated voltages This device contains protective circuitry against damage due to high static voltages or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated volta...

Page 409: ...alue of TAo 11 4 AC ELECTRICAL SPECIFICATION DEFINITIONS The AC specifications presented consist of output delays input setup and hold times and Signal skew times All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals The measurement of the AC specifications is defined by the waveforms shown in Figure 11 1 To test the parameters guaranteed ...

Page 410: ... Mechanical Data for the part numbering schemes MC68340 is used throughout this section to refer to the 16 78 or 25 16 MHz parts at 5 0 V 5 MC68340V is used throughout this section to refer to the 8 39 or 16 78 MHz parts at 3 3 V O 3 V MOTOROLA NOTE The electrical specifications in this section for the MC68340 25 16 MHz at 5 0 V 5 and the 3 3 V 0 3 V specifications for both the 8 39 and 16 78 MHz ...

Page 411: ...k 4 This input timing is applicable to all parameters specified relative to the falling edge of the clock 5 This timing is applicable to all parameters specified relative to the assertion negation of another signal LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time Specification E Signal valid to signal valid sp...

Page 412: ...BD mW Input Capacitance7 Cin pF Allinput Only Pins 10 All VOPins 20 load Capacitance7 CL 100 pF NOTES a The electrical spElCifications in this document for both the 8 39 and 16 78 MHz 3 3 V D 3 V are preliminary and apply only to the appropriate MC68340V low voltage part b The 16 78 MHz specifications apply to the MC68340 5 0 V 5 operation c The 25 16 MHz 5 0 V 5 electrical specifications are prel...

Page 413: ... 0 Hz 2 Assumes that a stable VCCSYN is applied that an external filter capacitor with a value of 0 1 jJ iEattached to the XFC pin and that the crystal oscillator is stable Lock time is measured from power up to R S T release This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register SYNCR while the PLL ...

Page 414: ...e input clock signal and the output CLKOUT signal from the MC68340 Clock skew is measured from the rising edges of the clock signals 12 For external clock mode w PLL there is a 5 ns skew between the input clock signal and the output CLKOUT signal from the MC68340 Clock skew is measured from the rising edges of the clock signals MOTOROLA MC68340 USER S MANUAL 11 7 ...

Page 415: ...sserted Write tSWAW 90 45 30 ns 14B AS CS iACKX and OS Read Width Asserted tSWDW 80 40 30 ns Fast Termination Cycle 153 AS OS CS Width Negated tSN 80 40 30 ns 16 CLKOUT High to AS OS RIW High Impedance tCHSl 120 60 40 ns 17 AS OS CS Negated to RIW High tSNRN 30 15 10 ns 18 CLKOUT High to RIW High tCHRH 0 60 0 30 0 20 ns 20 CLKOUT High to AMI Low tCHRL 0 60 0 30 0 20 ns 21 9 RIW High to AS CS Asser...

Page 416: ...Width Assarted Fast Termination Write or tRWAS 180 90 60 ns Read 47As Asynchronous Input Setup Time tAIST 15 8 5 5 ns 47B Asynchronous Input Hold Time tAIHT 30 15 10 ns 4s5 7 Asserted to BERR RACf Asserted tDABA 60 30 20 ns 53 Data Out Hold from CLKOUT High tOOCH 0 0 0 ns 54 CLKOUT High to Data Out High Impedance tCHDH 60 30 20 ns 55 RIW Asserted to Data Bus Impedance Change tRADC 80 40 25 ns 56 R...

Page 417: ...elects are used the CS width negated 1S applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select 4 These hold times are specified with respect to OS or CS on asynchronous reads and with respect to CLKOUT on fast termination reads The user is free to use either hold time for fast termination reads S H hedK1 chronous setup time 47 require...

Page 418: ...DO ASYNCHRONOUS INPUTS J so 81 83 S2 S4 85 9 K r I 14 CJ L IB N f I I r I I j 46 1 _ 1 J j II J I It L I f t t f f i I NOTE All timing is shown wi1h respect to O BV and 2 0V levels Figure 11 2 Read Cycle Timing Diagram MC68340 USER S MANUAL 11 11 ...

Page 419: ...4 C FC3 FCO rr S1Z1 SIZ0 rr to f K I 14 1 1 CD CDr f3 l Hfj p r I P I 1 k4 I f t t 015 00 f c f c III NOTE All timing is shown with respect to O 8 V and 2 0 V levels Figure 11 3 Write Cycle Timing Diagram 11 12 MC68340 USER S MANUAL MOTOROLA ...

Page 420: ...so Sl S4 S5 SO CLKOUT A31 AO FC3 FCO S1Z1 S1Z0 AS os CS 6A Rfi Figure 11 4 Fast Termination Read Cycle Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 13 ...

Page 421: ...so Sl S4 S5 SO CLKOUT A31 AO FC3 fCO SIZ1 SIZO AS OS CS ANi 015 00 BKPT Figure 11 5 Fast Termination Write Cycle Timing Diagram III 11 14 MC68340 USER S MANUAL MOTOROLA ...

Page 422: ...so 51 52 S3 S4 S5 ClKOUT A31 AO Dl5 DO AS t OS RiW DSACKO DSACK1 BR I BG BGACK Ec F t Figure 11 6 Bus Arbitation Timing Active Bus Case MOTOROLA MC68340 USER S MANUAL 11 15 ...

Page 423: ...1 Figure 11 7 Bus Arbitration Timing Idle Bus Case S41 S42 S43 so SI S2 CLKOUT A31 AO RiW AS os III 015 00 BKPT i SHOW CyCLE JJlo l START OF EXTERNAL CYCLE I Figure 11 8 Show Cycle Timing Diagram 11 16 MC68340 USER S MANUAL MOTOROLA ...

Page 424: ...T S1Z1 S1ZO FC3 fCO A31 NJ AS OS iACKi 18 Riii OSACKO OSACK1 015 00 Up to two wait states may be inserted by the processor between states SO and Sl Figure 11 9 lACK Cycle Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 17 ...

Page 425: ...ClKOUT FREEZE IFETCIWSI Figure 11 10 Background Debug Mode Serial Port Timing ClKOUT FREEZE Figure 11 11 Background Debug Mode FREEZE Timing III 11 18 MC68340 USER S MANUAL MOTOROLA ...

Page 426: ...0 ns 7 to DONE Assertion Skew 30 30 15 15 8 8 ns 8 AS DONE Width Asserted 200 100 70 ns 8A DONE Width Asserted Fast 80 40 28 ns Termination Cycle NOTES a The electrical specifications in this document for both the 8 39 and 16 78 MHz 3 3 V O 3 V are preliminary and apply only to the appropriate MC68340V low voltage part b The 16 78 MHz specifications apply to the MC68340 5 0 V S operation c The 25 ...

Page 427: ...5 8 ns ClKOUTlow 6 Asynchronous Input Setup Time to 10 5 3 ns ClKOUTHigh 7 Asynchronous Input Hold Time from 30 15 8 ns ClKOUTHigh 8 ClKOUT High to TOUT Valid tTO 3 60 3 30 3 20 ns NOTES a The electrical specifications in this document for both the 8 39 and 16 78 MHz 3 3 V O 3 V are preliminary and apply only to the appropriate MC68340V low voltage part b The 16 78 MHz specifications apply to the ...

Page 428: ...CLKOUT TIN TOUT _ _ I Figure 11 14 Timer Module Signal Timing Diagram III MOTOROLA MC68340 USER S MANUAL 11 21 ...

Page 429: ... Rx or tSH 11 TxD Data Valid from SCLK Low Synchronous tTxD 1 5 dTx Max 1 x Mode tcs Tx tVLD TX 12 RxD Setup Time to SCLK High Synchronous tRxS 0 5teydRx tCS Rx tCH Rx Min IX Mode 13 RxD Hold Time from SCLK High Synchronous tRxH 0 5teydRx tCS Rx tCH Rx Min 1x Mode NOTES a The electrical specifications in this document for both the 8 39 and 16 78 MHz 3 3 V O 3 V are preliminary and apply only to th...

Page 430: ...erial Module Asynchronous Mode Timing X1 SCLl 16x Figure 11 17 Serial Module Asynchronous Mode Timing SCLK 16X SClK lx TxD RxD Figure 11 18 Serial Module Synchronous Mode Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 23 ...

Page 431: ... 80 0 40 0 26 9 TCK Low to Output High Impedance 0 120 0 60 0 40 10 TMS TDI Data Setup Time 30 15 10 11 TMS TDI Data Hold Time 30 15 10 12 TCK Low to TOO Data Valid 0 50 0 25 0 16 13 TCK Low to TOO High Impedance 0 50 0 25 0 16 NOTES Unit MHz ns ns ns ns ns ns ns ns ns ns ns a The electrical specifications in this document for both the 8 39 and 16 78 MHz 3 3 V G 3 V are preliminary III and apply o...

Page 432: ...LID DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS TCLK TOI TMS TOO TOO TOO OUTPUT DATA VALID OUTPUT DATAVALID Figure 11 20 Boundary Scan Timing Diagram IN UT DATA VAUD OUTPUT DATAVAll OUTPUTDATA VALID Figure 11 21 Test Access Port Timing Diagram MC68340 USER S MANUAL 11 25 ...

Page 433: ...III 11 26 MC68340 USER S MANUAL MOTOROLA ...

Page 434: ...40FE16 FE Suffix 0 16 78 40 C to 8S C MC68340CFE16 0 25 O Cto 70 C MC68340FE2S S OV Plastic Pin Grid Array 0 16 78 OOCto 70 C MC68340RP16 RP Suffix 0 16 78 40 C to 8S C MC68340CRP16 0 25 OOCto 70 C MC68340RP2S 3 3 V Ceramic Quad Flat Pack 0 8 39 O Cto 70 C MC68340FE8V FE Suffix 0 8 39 40 C to SS C MC68340CFE8V 0 16 78 O Cto 70 C MC68340FE16V 3 3 V Plastic Pin Grid Array 0 8 39 O Cto 70 C MC68340RP...

Page 435: ...KOUT Vee XFC Vee EXTAL VCCSVN XTAL GND MOOCK Vee iffiCj j BKPT FREEZE TINI TOUT TGATE1 TCK TMS TOI TOO Vee GND 12 2 MC68340 USER S MANUAL cso CSI CS2 IROO CS3 GND Vee IROS 1R l6 1RQ7 iiONE2 DACK2 iiREli DONE1 mKr DREQ1 Xl GND Vee X2 SCLK CTsB RTSB TxIlB AxDB TxRDVA RiiiDYA CTSA RTSA GND Vee TxDA RxDA TIN2 TOUT2 TGATE2 MOTOROLA ...

Page 436: ...fix package Pin Group FE Suffix vec GND Address Bus Fundion Codes 41 50 59 68 134 42 51 60 69 135 Data Bus 113 123 114 124 AS Em CLKOUT FREEZE RArf TFE fCH TPlPE 15 17 35 143 13 21 36 144 MODCK RESET RMC RIW SIZx TOO TOUT1 Internal Logic DACRi 00NEi TROx RTSx RxRDYA TOUT2 78 90 102 79 91 103 TxDx TxRDYA Internal Logic Oscillator 19 Internal Only 23 55 126 MOTOROLA MC68340 USER S MANUAL 12 3 EI ...

Page 437: ...J 000 A14 A15 GNO H 000 A12 A13 GND GOO 0 All GNo Vee F 000 Al0 A9 AS E 000 A7 A6 AS o 000 0 BOTTOM VIEW MC68340 000 Vee AD A30 000 A31 A29 A28 000 GNo Vee A27 000 A25 A24 A26 000 GNO 014 015 000 GNo 012 013 000 Vee 011 010 000 07 os 09 000 A4 Vee GNO NC GNo 05 D6 cOO 0 000 000 0 0 0 0 0 0 AS A2 TGATE2 Vee GNO TxOB Vee GNO OACKl IRQ7 GNo CS2 01 Vee D4 BOO 0 000 000 0 0 0 0 0 o A r6lT 2 A SA Rx YA ...

Page 438: ... package Pin Group RP Suffix Vec GND Address Bus Function Codes 02 G3 K3 K14 M3 03 G2 J3 K13 M2 Oata Bus C14 F13 013 G13 AS M ClKOUT FREEZE HArF lFE fCH M13 N4 N9 P9 N3 N7 N10 N13 MOOCK RESET RMC RIW SIZX TOO TOUT1 Internal logic DmiiEi lROx R i Sx RiR 5VA TOUT2 TxOx B11 C4 C7 C5 C8 C11 I iR DVA Internal logic Oscillator N8 Internal Only P7 H3 H13 MOTOROLA MC68340 USER S MANUAL 12 5 ...

Page 439: ...70 0 009 0 016 0 0256 BASIC 0 010 0 035 0 005 0 010 0 026 0 037 o s 0 0128 BAS1C O 02S 1 219 1 238 1219 1 238 NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION MILLIMETERS 3 DIM AAND BDEFINE MAXIMUM CERAMIC BODY DIMENSIONS INCLUDING GLASS PROTRUSION AND MISMATCH OF CERAMIC BODY TOP AND BOTTOM 4 DATUM PLANE W IS LOCATED AT THE UNDERSIDE OF LEADS WHERE LEADS EXIT PACK...

Page 440: ... 1 550 1 570 1 550 1 570 0 885 0 905 0 885 0 905 0 100 BASIC 0 115 J 0 135 0 040 J 0 060 nn17 I 0 170 I 0 185 1 1 400BASIC sl Q 000000000000 L T P 6 0 0 0 0 0 0 0 0 0 0 ORMdHl N 000000000000000 T M 000 000 L 000 000 K 000 000 J 000 BOTIOM 000 H 000 VIEW 000 G 000 000 V F 000 000 L E 000 000 D 0000 000 A 0000000000000A 4 lr Ie 0000000000000 0 B 0 6 0000000000000 1 2 3 4 5 8 7 8 9 10 1112131415 M145...

Page 441: ...12 8 MC68340 USER S MANUAL MOTOROLA ...

Page 442: ...ate Clock 7 2 7 26 7 27 Generator 7 3 7 8 BB Bits 6 4 6 29 6 38 BDM Sources 5 66 BED Bit 6 27 6 27 6 30 6 31 6 37 BERR Signal 5 45 5 47 BES Bit 6 20 6 31 6 37 BFC Bits 4 30 BGND Instruction 5 66 Binary Coded Decimal Extended Instructions Timing Table 5 106 Instructions 5 26 Bit Manipulation Instructions 5 25 Timing Table 5 109 Bit Set Reset Command 7 37 Bits per Character 7 23 BKPT Signal 5 65 5 6...

Page 443: ...7 27 7 46 7 47 Sequence Diagram 5 74 5 75 Compare Register 8 2 8 12 8 26 8 27 Compressed Tables 5 31 5 32 Condition Code Register 5 10 5 14 5 20 5 21 Condition Codes 5 10 5 26 5 27 Condition Test Instructions 5 20 5 21 5 29 Conditional Branch Instruction Timing Table 5 110 CONF Bit 6 20 6 30 6 31 6 37 6 38 Configuration Code Modules SIM40 4 38 4 40 DMA 6 38 6 45 Serial 7 47 4 49 Timer 8 28 8 31 Co...

Page 444: ...6 29 6 37 DSO Signal 5 69 5 71 Dual Address Destination Write 6 15 Mode 6 12 6 28 6 37 Source Read 6 12 Transfer 6 3 Dump Memory Block Command 5 80 5 81 Dynamic Bus Sizing 3 5 3 14 E Early Bus Error 3 34 EBI 4 2 4 22 4 33 ECO Bit 6 7 6 27 6 28 6 37 Effects of Wait States on Instruction Timing 5 92 Electrical Characteristics 11 1 AC Electrical Specifications Definitions 11 2 11 4 Control Timing 11 ...

Page 445: ... 19 7 1 8 1 Immediate Arithmetic Logical Instruction Timing Table 5 105 IN Bit 5 53 5 56 5 61 Input Port 7 35 Change Register 7 31 Instruction Cycles 5 97 Execution Overlap 5 91 5 92 5 94 5 95 Execution Time Calculation 5 92 5 93 Fetch Signal 2 19 Heads 5 91 5 94 5 97 Pipe Signal 2 10 Pipeline Operation 5 89 5 90 5 93 Register 9 9 9 1 Stream Timing Examples 5 94 5 97 Tails 5 91 5 94 5 97 Timing Ta...

Page 446: ... 59 5 61 MOVEP Faults 5 55 5 56 Multidrop Mode 7 15 7 16 7 23 Timing 7 16 Multiprocessor Systems 5 61 N NCS Bit 4 31 Negate RTS Command 7 29 Negative Tails 5 93 5 94 No Operation Command 5 86 0 OC Bits 8 6 8 8 8 10 8 22 8 28 OE Bit 7 13 7 25 7 28 ON Bit 8 6 8 8 8 11 8 24 One Mode 8 23 OPO 7 6 7 36 7 38 OP1 7 7 7 36 7 38 OP4 7 7 7 36 7 37 OP6 7 7 7 36 7 37 Opcode Tracking in Loop Mode 5 88 Operand ...

Page 447: ...tion 3 36 Interruption 3 36 3 43 Operation 3 4 Read Modify Write Signal 2 8 3 19 3 21 3 40 3 42 3 43 3 45 Read Write Signal 2 7 3 2 Real Time Clock 4 9 Receive Data Signal 2 11 Received Break 7 11 7 24 7 33 Receiver 7 9 7 11 Baud Rates 7 26 Buffer 7 11 7 12 7 25 7 30 Disable Command 7 30 Enable Command 7 30 FIFO 7 12 7 13 7 17 7 22 7 23 7 25 7 33 7 34 Holding Registers 7 9 7 11 Ready Signal 2 12 S...

Page 448: ... Breakpoints 5 53 5 54 Interrupt Vector Register 4 7 4 24 4 36 Operation 4 4 4 6 4 17 4 27 Service Register 4 7 4 28 Service Routine 4 7 4 25 Timeout 4 25 Watchdog 4 1 4 4 4 6 Watchdog Clock Rate 4 7 Source Address Register 6 7 6 12 6 18 6 19 6 28 6 33 6 37 6 38 Special Status Word 5 45 5 52 Special Purpose MOVE Instruction Timing Table 5 101 5 102 Spurious Interrupt 3 29 Monitor 4 1 4 4 4 6 4 17 ...

Page 449: ... Two Clock Bus Cycles 10 3 TxCTS Bit 7 39 7 47 TxDx Signal 7 3 7 6 7 10 7 14 7 29 TxEMP Bit 7 10 7 25 7 28 TxRDY Bit 7 10 7 25 7 28 7 31 TxRDYA Bit 7 34 7 35 TxRDYA Signal 7 7 7 36 TxRDYB Bit 7 33 7 35 TxRTS Bit 7 38 7 47 Types of DMA Interrupts 6 20 U Unimplemented Instructions 5 12 Emulation 5 74 Exception 5 48 5 50 UNLK Instruction 5 36 Use of Chip Selects 4 15 10 3 10 4 User Privilege Level 5 ...

Page 450: ... y Y Bits 4 12 4 13 4 28 4 36 z Zero Mode 8 23 MOTOROLA MC68340 USER S MANUAL Index 9 ...

Page 451: ...Index 10 MC68340USER S MANUAL MOTOROLA ...

Page 452: ...ial decode for any access to this range but selection of specific registers depends on additional decode Accesses to the MBAR register at long word 3FFOO are internal only and are only visible by enabling show cycles Users should directly access only the MBAR register and use the LPSTOP instruction to generate the LPSTOP broadcast access to 3FFFE The remaining address range 3FF04 3FFFD is Motorola...

Page 453: ...ector Interrupt Acknowledge Cycle section on page 3 29 If an external interrupt level is autovectored either by the AVEC register programming or the external AVEC signal an external lACK will be started and terminated internally The interrupting device should not respond to this lACK in any way or the resulting operation is undefined 9 Additional Notes on Retry Termination On page 3 33 Table 3 4 W...

Page 454: ...nitor operates whether it is enabled or not for the period of time that the BMT bits are set to The following reset sources reset all internal registers to their reset state external POR software watch dog double bus fault loss of clock Execution of a RESET instruction resets the peripheral module registers serial DMA timers with the exception of the MCR registers The MCR register in each module t...

Page 455: ...n italics for VCO operation with a32 768KHz crystal oscillator circuit Figure 4 4 Clock Block Diagram for Crystal Operation 19 Recommended XFC capaCitor values x On page 4 12 second paragraph and page 10 2 last paragraph The XFC capacitor recommendation of 0 01 F to 0 1 F applies specifically to crystal mode operation When using external clock with VCO mode for frequencies 1MHz start with a capaci...

Page 456: ...eplaced by the following full table of frequencies Note that although a complete table is shown for all W X Y combinations both CLKOUT and VCO frequency limits must be ob served when programming the SYNCR For example a system operating frequency CLKOUT of 25 16MHz can be selected with W X Y 1 1 23 resulting in a VCO frequency of 50 3MHz However pro gramming W X Y 1 0 47 to achieve the same system ...

Page 457: ... 12845 25690 25690 51380 102760 17 2359 4719 9437 9437 18874 37749 49 6554 13107 26214 26214 52429 104858 18 2490 4981 9961 9961 19923 39846 50 6685 13369 26739 26739 53477 106955 19 2621 5243 10486 10486 20972 41943 51 6816 13631 27263 27263 54526 109052 20 2753 5505 11010 11010 22020 44040 52 6947 13894 27787 27787 55575 111149 21 2884 5767 11534 11534 23069 46137 53 7078 14156 28312 28312 56623...

Page 458: ... 21 for the second code sequence change the MOVE L FFFFF001 DO to MOVE L FFFFF1 01 DO This sets AS7 in the MBAR to prevent the address decode for the internal 4K register block from responding to CPU space accesses In particular it prevents the register block decode of FFFFFxxx from interfering with lACK cycles address FFFFFFFx and possibly corrupting the vector number returned Normal interrupt ac...

Page 459: ...ally asserts for an additional 0 5 ClKs IPIPE transitions occur after the falling edge of ClKOUT 34 Additional Notes on OMA Features In the feature set listed on page 6 1 bullet five is Operand Packing and Unpacking for Dual Address Trans fers This packing is for transfers between different port sizes selected in the DMA channel control register e g Byte Word transfers The DMA controller does not ...

Page 460: ...lowing table for various memory speeds Table 1 DREQ Latency Clocks vs Bus Width and Access Times Maximum DREQ Latency Clocks Access Type 16 Bit Bus 8 Bit Bus Clocks Bus Cycle Clocks Bus Cycle 2 3 4 5 2 3 4 5 Longword 7 9 11 13 11 15 19 24 RMC TAS 10 12 14 16 10 12 14 16 39 Additional Note on Burst Transfer DREQ Negation and Overhead Replace the 2nd paragraph of 6 3 2 1 External Burst Mode with the...

Page 461: ...g to the destination size not the source size 47 Additional note on DMA limited rate operation On page 6 29 in the BB Bus Bandwith Field The DMA active count increments only when the DMA channel is the bus master each channel has its own counter If a higher priority bus master forces the channel to relinquish the bus before completion of the active count the counter stops until the channel regains...

Page 462: ... Writing a 1 to the corresponding bit in the OPRESET register 71 F Issuing a Negate RTS command using command register CR If RxRTS l cleared by receiver FIFO transition from not FULL to FULL If TxRTS l cleared by completion of last character including transmission of stop bits 52 Serial Frequency Restriction Suffix B and Earlier On page 7 8 place the following notes at the end of Section 7 3 1 Bau...

Page 463: ...caled depending on the maximum baud rate selected Operation and specifications for external clocking via SCLK are not affected by this change The table below shows the resulting minimum CLKOUT frequency for each programmable baud rate Note that applications using the VCO clock modes crystal and external clock with VCO are restricted to a 131 KHz minimum CLKOUT frequency An errata exists which also...

Page 464: ... Once this transfer occurs as indicated by the TxRDY assertion the AID bit in MR1 can be changed without affecting the character in progress The proper programming sequence to change the AID bit for the next character would be 1 poll TxRDY until asserted or interrupt on TxRDY 2 set clear AID bit in MR1 for new character 3 write character to transmit buffer TB 4 AID bit can be changed only after Tx...

Page 465: ...REQ1 see notes on DREQ1 and serial oscillator for p 7 15 Place a ground shield around the oscillator logic use a separate trace for ground to the oscillator so that it does not carry any of the digital switching noise 61 Recommended 32KHz Oscillator Circuit On page 10 2 Figure 10 2 the component values shown in the example 32KHz oscillator circuit may not provide enough loop gain for all crystals ...

Page 466: ...time delay of 328 Tclkin does not provide adequate time for VCC to stabilize before allowing reset to negate Applications using these two clocking modes should include an external reset circuit which generates an appropriate delay for the power source being used as well as a voltage monitor if needed Note that beginning with 1F77J silicon C suffix parts the delay for external clock with VCO mode h...

Page 467: ...ecifications The Clock Input High Voltage spec applies to both the EXTAL and X1 inputs 68 Input Clock Duty Cycle in External Clock w PLL mode On page 11 6 Note 7 at the bottom The input clock 20 80 duty cycle for external clock with PLL mode can be used when the VCO is not turned off during LPSTOP During LPSTOP with the VCO turned off the input clock is used for clocking the SIM and must meet the ...

Page 468: ... C MC68340PV16V PV Suffix 0 8 39 0 C to 70 C MC68340PV8V 3 3 V Ceramic Quad Flat Pack 0 8 39 0 C to 70 C MC68340FE8V FE Suffix 0 8 39 40 C to 85 C MC68340CFE8V 0 16 78 0 C to 70 C MC68340FE16V 3 3 V Plastic Pin Grid Array 0 8 39 0 C to 70 C MC68340RP8V RP Suffix 0 8 39 40 C to 85 C MC68340CRP8V 0 16 78 0 C to 70 C MC68340RP16V 71 TxRDY RxRDY Pin Swap Add to the Pin Assignment section beginning pag...

Page 469: ...IROS BG IR06 BR IRO BERR DONE2 HALT DACK2 RESET DRE02 GND DONE1 CLKOUT DACK1 VCC ORE01 XFC X1 VCC GND EXTAL VCC VCCSYN X2 XTAL SCLK GNO CTSB MODCK RTSB VCC TxDB IPIPE RxDB IFETCH TxRDYA BKPT RxRDYA FREEZE CTSA TIN1 RTSA TOUT1 GND TGATE1 VCC TCK TxDA TMS RxDA TDI TIN2 TOO TOUT2 VCC TGATE2 GND c U 2 0 c U C P ClUt oo H f2 t5 c t5 z c c c t5 18 MC68340 USER S MANUAL ADDENDUM MOTOROLA ...

Page 470: ...EF nt w NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1962 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY ATTHE BOTTOM OF THE PARTING LINE 4 DATUMS L M AND N TO BE DETERMINED AT DATUM PLANE H 5 DIMENSIONS SAND VTO BE DETERMINED AT SEATING PLANE T _ 6 DIMENSIONS AAND BDO NOT INCLUDE MOLD PR...

Page 471: ...personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees aris ing out of directly or indirectly any claim of personal injury or dea...

Page 472: ... injury ordeath may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associa...

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