Motorola M68MPBF333, User Manual

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MEVB SUPPORT INFORMATION
4-10 M68MPB333UM/D
Table 4-11. Logic Analyzer Connector J17 Pin Assignments (continued)
Pin Mnemonic Signal
12 PCS0 /
SS
PERIPHERAL CHIP SELECT 0 – Active-low output
SPI peripheral chip select signal.
SLAVE SELECT – Bi-directional, active-low signal that
initiates serial transmission when SPI is in slave mode;
causes mode fault in master mode.
13 SCK SPI SERIAL CLOCK – In master mode, the clock
signal from the SPI; in slave mode the clock signal to
the SPI.
14 MOSI MASTER-OUT, SLAVE-IN – Serial output from SPI in
master mode; serial input to SPI in slave mode.
15 MISO MASTER-IN, SLAVE-OUT – Serial input to SPI in
master mode; serial output from SPI in slave mode.
16 GND GROUND
17 – 19 SPARE No connection
20 GND GROUND
Table 4-12. Logic Analyzer Connector J18 Pin Assignments
Pin Mnemonic Signal
1 – 4 SPARE No connection
5 VSSA A/D GROUND – A/D ground reference.
6 – 9 AN0 – AN3 ANALOG INPUT 0 –3 – Analog input line to the MCU
device.
10 VRL VOLTAGE REFERENCE LOW – Input reference
supply voltage (low) line (must set jumper on the MPB).