MEVB SUPPORT INFORMATION
M68MPB333UM/D
4-7
Table 4-7. Logic Analyzer Connector J13 Pin Assignments (continued)
Pin
Mnemonic
Signal
7
DS
DATA STROBE – Active-low output signal. During a
read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
8
BR /
CS0
BUS REQUEST – Active-low input signal that indicates
an external device requires bus mastership.
CHIP SELECT 0 – Output signal that selects peripheral
or memory devices at programmed addresses.
9
BG /
CSM
BUS GRANT – Active-low output signal that indicates
the MCU has relinquished the bus.
INTERNAL MODULE CHIP SELECT – CSM is not
supported on the MC68F333 MCU.
10
CSBOOT
BOOT CHIP SELECT – An active-low output chip
select for external boot startup ROM
11
CLKOUT
SYSTEM CLOCK OUTPUT – MCU internal clock
output signal.
12
A23 /
CS10
ADDRESS BUS BIT 23 – One bit of the 24-bit address
bus.
CHIP SELECT 10 – Output signal that selects
peripheral or memory devices at programmed
addresses.
13
A22 /
CS9
ADDRESS BUS BIT 22 – One bit of the 24-bit address
bus.
CHIP SELECT 9 – Output signal that selects peripheral
or memory devices at programmed addresses.
14
A21 /
CS8
ADDRESS BUS BIT 21 – One bit of the 24-bit address
bus.
CHIP SELECT 8 – Output signal that selects peripheral
or memory devices at programmed addresses.
15
A20 /
CS7
ADDRESS BUS BIT 20 – One bit of the 24-bit address
bus.
CHIP SELECT 7 – Output signal that selects peripheral
or memory devices at programmed addresses.
