User Guide
Designer Reference Manual
DRM028 — Rev 0
140
User Guide
MOTOROLA
#define CURR_PIREG_I_GAINSCALELEFT 0
Range: <0,8>
/* MUST_CHANGE_5_EXPER: */
#define CURR_PIREG_I_GAIN 64
Range: <0,255>
where the current regulator integral gain is:
KP = CUR_PIREG_I_GAIN*2
CURR_PIREG_I_GAINSCALELEFT
(EQ 6-5.)
These constants can be calculated according to regulators theory. The
current sampling (regulator execution) period is
PER_CS_T1_US
= 128
µ
s, at the default software setting. Normally it does not need to be
changed (if change is required see
PWM Frequency and Current
Sampling Period Setting
). Another recommended solution is an
experimental setting.
NOTE:
CURR_PIREG_P_GAINSCALELEFT, CURR_PIREG_P_GAIN,
CURR_PIREG_I_GAINSCALELEFT, CURR_PIREG_I_GAIN can be
evaluated with PC master software tuning file tuning_bldc.pmp.
We suggest using PC master software with tuning file tuning_bldc.pmp
for regulator parameters evaluation. You can use this procedure:
1. Set
const_cust_x.h
:
CURR_PIREG_P_GAINSCALELEFT
0
CURR_PIREG_P_GAIN 0
CURR_PIREG_I_GAINSCALELEFT 0
CURR_PIREG_I_GAIN 0
2. Temporarily change the software: in
code_start.c
file, label
TUNING_1 enable goto Align (it will cause infinite time for
alignment state, where the current is tuned)
3. Build and run the code (see
Software Execution
,
Build
,
Execute
from Evaluation Board
)
4. Start the PC master software tuning project
5. Select Current Parameters Tuning subproject (see
Software
Parameters Tuning with PC Master Software Project File
) in
order to be able to modify the current regulator
6. You can see the actual current (and required alignment current)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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