MOTOROLA
TIMER/RESET MODULE
MMC2001
9-14
REFERENCE MANUAL
9.6.5 PIT Control/Status Register (ITCSR)
Figure 9-16 PIT Control and Status Register
Access this register with 32-bit loads and stores only.
STOP — Stop Mode Control
This bit controls the function of the PIT in stop mode
0 =
PIT function is not affected in stop mode
1 =
PIT function is frozen in stop mode
DOZE — Doze Mode Control
This bit controls the function of the PIT in doze mode
0 =
PIT function is not affected in doze mode
1 =
PIT function is frozen in doze mode
DBG — Debug Mode Control
This bit controls the function of the PIT in debug mode
0 =
PIT function is not affected in debug mode
1 =
PIT function is frozen in debug mode
OVW — Counter Overwrite Enable
This bit controls what happens to the counter value when the modulus latch is written.
0 =
Modulus latch is a holding register for values to be loaded into the counter
when the count expires to zero.
1 =
Modulus latch is transparent. All writes to the latch will also overwrite the
counter contents.
ITIE — PIT Interrupt Enable
This bit controls the PIT interrupt function.
0 =
ITIF is inhibited from reaching the CPU.
1 =
ITIF is allowed to request an interrupt.
ITIF — PIT Interrupt Flag
This bit is the PIT interrupt flag. It is cleared by writing a one to this bit or by writing to
the PIT data register.
0 =
No PIT interrupt is present
1 =
PIT interrupt is present
ITCSR — Interval Timer Control and Status Register
10001024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
STOP DOZE
DBG
OVW
ITIE
ITIF
RLD
EN
W
RESET:
0
0
0
0
0
0
0
0
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