Motorola DSP56F803, Hardware User Manual

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2-4 DSP56F803EVM Hardware User’s Manual
2.2 Program and Data Memory
The DSP56F803EVM uses one bank of 128K
×
16-bit Fast Static RAM (GSI GS72116,
labelled U2) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-1 . This physical memory bank is split into two logical memory banks of
64Kx16-bits: one for Program memory and the other for Data memory. By using the
DSP’s program strobe, PS, signal line along with the memory chip’s A0 signal line, half of
the memory chip is selected when program memory accesses are requested and the other
half of the memory chip is selected when data memory accesses are requested. This
memory bank will operate with zero wait-state accesses while the DSP56F803 is running
at 70MHz. However, when running at 80MHz, the memory bank operates with four
wait-state accesses. This memory bank can be disabled by removing the jumper at JG5.
Figure 2-1. Schematic Diagram of the External Memory Interface
DSP56F803 GS72116
A0-A15
PS
D0-D15
RD
WR
A1-A16
A0
D0-D15
RD
WR
CS
1 2
JG5
+3.3V
Connect Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM