Motorola CPIP5430 Page 52 Installation And Use Manual Download | Manualshive

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BIOS

3

IDE Configuration Utility

The following sections describe the configuration options for the IDE
controller.

IDE Configuration Descriptions

IDE CONFIGURATION UTILITY

IDE CONFIG

PRIMARY MASTER

PRIMARY SLAVE

SECONDARY MASTER

SECONDARY SLAVE

IDE Configuration P-ATA only

P-ATA Channel Selection Both

Hard Disk Write Protect Disabled

IDE Detect Time Out (Sec) 35

Onboard IDE Drive Pin Count 40

↑

↓

Select Screen

↑

↓

/+- Change Option

F1 General Help Esc Exit

Motorola CPIP5430 BIOS v1.00 Beta-M

IDE Configuration

Selects the configuration for the onboard parallel and serial IDE controllers.

Combined Mode
Option

Selects which IDE connectors are active. When set to P-ATA Primary, the
on-board parallel drive is set as the primary master, and the serial ATA
connector on the Rear I/O board is set to secondary master. The parallel
ATA connector on the Rear I/O is disabled in this mode. When set to S-ATA
primary, the serial ATA connector on the Rear I/O is set to primary master,
and the parallel ATA connector on the Rear I/O is set to the secondary
master/slave. The onboard parallel drive is disabled in this mode.

Hard Disk Write
Protect

When this item is enabled, the BIOS protects the IDE drives from write
accesses. This is only effective for operating systems that access the hard
drives using BIOS interfaces.

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Summary of Contents for CPIP5430

Page 1: ...CPIP5430 Single Board Computer and Transition Module Installation and Use CPIP5430A IH2 June 2004 Edition ...

Page 2: ...ogo are trademarks of Motorola Inc registered in the U S Patent and Trademark Office All other product or service names mentioned in this document are the property of their respective owners PICMG CompactPCI and the PICMG and CompactPCI logos are registered trademarks of the PCI Industrial Computer Manufacturers Group ...

Page 3: ...the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power ...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Caution Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constr...

Page 5: ...ola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the docu...

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Page 7: ...derations 1 7 Insertion 1 7 Extraction 1 7 Hardware Installation 1 8 Configuring Headers 1 8 Jumpering Diagram for Header E4 1 8 Jumpering Diagram for Header E1 1 9 Memory Module Installation 1 9 2 5 inch HDD Installation 1 11 PCI Mezzanine Card Installation 1 13 Before You Install a Board 1 15 Installing a Board 1 15 CPIP5430 Hot Swap Module Removal 1 18 CHAPTER 2 Startup and Operation Applying P...

Page 8: ...uration Summary 3 13 Hard Drive Setup Descriptions 3 14 Boot Order 3 15 Boot Order Descriptions 3 16 Peripherals 3 17 Peripherals Descriptions 3 18 Console Redirection Descriptions 3 19 USB Configuration 3 20 USB Control Descriptions 3 21 USB Mass Storage Configuration Descriptions 3 21 Misc Configuration 3 22 PCI and PNP Configuration Summary 3 22 PCI Options Descriptions 3 23 PnP Options Descrip...

Page 9: ...rt COM2 5 4 USB Interface 5 4 IDE Interface 5 4 I2C Interface 5 5 Preparing the RTM 5 5 Installing the RTM 5 7 CPIP5430 RTM Transition Module Installation 5 7 Pin Assignments 5 9 User I O Connector J5 5 9 PMC Connectors 5 11 40 Pin IDE Connector 5 14 COM2 5 16 USB Port 2 5 16 Ethernet Connector 5 17 CompactFlash 5 17 Serial ATA 5 19 CHAPTER 6 Connector Pin Assignments PCI Mezzanine PMC Connectors ...

Page 10: ...on Temperature B 3 Measuring Case Temperature B 3 Measuring Local Air Temperature B 6 APPENDIX C Memory Maps Memory Maps C 1 PCI Configuration Mapping C 2 SMBUS Address Map C 3 IPMB Address Map C 4 PCI Interrupt Connections C 5 Sensor Data Record C 6 APPENDIX D IPMI Commands Introduction D 1 SDR Sensor Data Record Device Commands D 1 APPENDIX E Related Documentation Motorola Computer Group Documen...

Page 11: ... CPIP5430 RTM1 Block Diagram 5 2 Figure 5 2 CPIP5430 RTM1 Layout 5 6 Figure 5 3 Serial ATA Connection Pin Assignment 5 19 Figure B 1 Thermally Significant Components Primary Side B 2 Figure B 2 Mounting a Thermocouple Under a Heatsink B 5 Figure B 3 Measuring Local Air Temperature B 6 List of Figures ...

Page 12: ......

Page 13: ...mpactFlash Connector 5 17 Table 6 1 PMC Connector J9 J11 Pin Assignments 6 1 Table 6 2 PMC Connector J5 J7 Pin Assignments 6 3 Table 6 3 PMC Connector J8 J10 Pin Assignments 6 5 Table 6 4 PMC Connector J6 Pin Assignments 6 7 Table 6 5 Power Connector J1 Pin Assignments 6 9 Table 6 6 Ground Connector J2 Pin Assignments 6 10 Table 6 7 User I OJ3 Connector Pin Assignments 6 11 Table 6 8 User I O J5 C...

Page 14: ...SMBUS Address Map C 3 Table C 4 CompactPCI Peripheral Address Map C 4 Table C 5 PCI Interrupt Connections C 5 Table C 6 Sensor Data Record List C 6 Table E 1 Related Documents E 1 Table E 2 Related Specifications E 1 ...

Page 15: ... CPIP5430 2232 K CPIP5430 2232 F Intel Pentium 4 CPU 2 16 I O 1 7GHz 1GB 2x512MB memory 1HDD CPIP5430 2241 K CPIP5430 2241 F Intel Pentium 4 CPU 2 16 I O 1 7GHz 2GB 2x1GB memory CPIP5430 2242 K CPIP5430 2242 F Intel Pentium 4 CPU 2 16 I O 1 7GHz 2GB 2x1GB memory 1HDD CPIP5430 4231 K CPIP5430 4231 F Intel Pentium 4 CPU 2 16 I O 2 2GHz 1GB 2x512MB memory CPIP5430 4232 K CPIP5430 4232 F Intel Pentium...

Page 16: ...in an MXP series chassis Chapter 2 Startup and Operation provides the power up procedure identifies the switches and indicators and explains how to generate a soft reset on the CPIP5430 Chapter 3 BIOS provides a description of the BIOS on the CPIP5430 CPIP5430 4452 K CPIP5430 4452 F Intel Pentium 4 CPU 2 16 I O 2 2GHz 4GB 2x2GB memory 1HDD CPIP5430 MEM1 K Memory 512MB Max 2 per CPIP5430 CPIP5430 M...

Page 17: ...mally significant components along with their maximum allowable operating temperatures Appendix C Memory Maps provides memory maps for the CPIP5430 Appendix D IPMI Commands provides commands that may be used by a host device driver and or application software to communicate with the Zircon sensors and other management controllers in the system Appendix E Related Documentation provides a listing of...

Page 18: ...ars it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values for function parameters and for structure names and fields Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports exa...

Page 19: ...ontroller features a single Mobile P4 Processor M with 512KB L2 cache 400 MHz to 800 MHz Front Side Bus FSB speed and 266 MHz to 400 MHz DDR via two SODIMM sockets The CPIP5430 features both an Intel 82547 Gigabit Ethernet GbE controller that can be configured for either front panel or rear transition module access and an Intel 82546EB dual port Gigabit Ethernet GbE controller These dual GbE conne...

Page 20: ...nd or CD DVD drive or IDE CD DVD drive Connecting cables Overview of Startup Procedures The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read this entire chapter including all Caution and Warning notes before you begin Table 1 1 Startup Overview What you need to do Refer to Unpack...

Page 21: ...ommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system Electronic components such as disk drives computer boards and memory modules can be extremely sensitive to electrostatic discharge ESD After removing the component from its protective wrapper or from the system place the component flat on a grounded static free surface and in the case of ...

Page 22: ...ng this card you should review the specifications of any chassis and backplane intended to house the CPIP5430 to determine the presence of and any limitations of the IPMI bus switched Ethernet and user defined pinouts As an example some chassis backplanes route certain I O pins to internal resources such as alarm cards drive resources or route PCI signals to failover circuitry or extension bridges...

Page 23: ...ble Table 1 2 CPIP5430 Connectors and Headers Reference Designator Description J1 Backplane connector power CPCI control IPMI ground J2 Backplane connector ground CPCI control J3 Backplane connector User I O J5 Backplane connector User I O J18 IDE connector 44 pin J17 Serial COM1 connector RJ45 8 pin J16 Ethernet connector RJ45 8 pin connector J14 USB connector 4 pin for development service and se...

Page 24: ...nine connector 64 pin J5 PCI mezzanine connector 64 pin E4 Ethernet signal header 4 pin E1 12V power for RTM USB control Table 1 2 CPIP5430 Connectors and Headers continued Reference Designator Description 4263 0304 J5 J3 J2 J1 PMC2 U27 J13 U28 U22 J9 J5 J8 RST U18 USB J14 U30 HS PMC1 J11 J7 J10 J6 J12 J18 U25 U26 U29 U21 U23 J17 COM1 J16 ENET ...

Page 25: ...load slot on the backplane The blue LED is illuminated When fully seated the ejector levers are closed at which point the blue LED should go off after a short delay due to the IPMI controller The system starts to boot Extraction Following are the stages of extraction for a CPIP5430 When the ejector lever is opened the IPMI control circuitry is signalled The IPMI satellite controller communicates w...

Page 26: ... memory modules and hard drives are already in place on the base board The user configured jumper E4 is not easily accessible with a module installed If you need to place a jumper removing the module may be necessary Should it be necessary to install modules on the base board refer to PCI Mezzanine Card Installation for a description of the procedure Configuring Headers The following headers that ...

Page 27: ...pends upon a proprietary memory module and specialized signal routing to obtain densities of 2GB per SODIMM socket All standard DDR SODIMM modules are compatible however 2GB is only achievable with the purchase of a special memory module Jumper Function Setting E4 Reserved Routes Ethernet signal to the RTM Routes Ethernet signal to the CPIP5430 front panel 1 2 jumper off 3 4 jumper on 3 4 jumper o...

Page 28: ...e parameters of the slowest installed DDRs The DDR interface supports 128Mb 256Mb and 512Mb technology which allows up to 1GB per double sided SODIMM The CPIP5430 supports up to 4GB of SDRAM memory with two 144 pin SO DIMMs The memory configurations are summarized in the following table The CPIP5430 has been tested with 128MB 256MB 512MB 1GB and 2GB registered ECC SODIMM modules To install the mem...

Page 29: ...P5430 controller instead of a standard PMC if not already installed from the factory The following procedure describes how to mount a 2 5 inch hard disk drive on one of the PMC sites of the CPIP5430 If the CPIP5430 is currently installed in a system chassis perform the following steps 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground Keep the ESD ...

Page 30: ...he second PMC slot 6 Bolt the carrier rails onto the sides of the 2 5 HDD The flange on each rail should be facing away from the drive 7 Attach the 44 pin IDE cable to the drive 8 Install the drive assembly onto the top side of the board and tighten the four screws from the bottom side of the board to secure the drive firmly avoid overtightening 9 Connect the 44 pin IDE cable to the J18 IDE connec...

Page 31: ...lowing steps If you are installing a PMC on a board that has not yet been installed in a chassis begin with step 6 Some devices such as IDE connector components may restrict proper seating of PMCs that populate the PMC1 site If this occurs do not attempt to install a PMC on that site 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground Keep the ESD s...

Page 32: ...IO keying pin 8 Insert the four screws through the holes on the bottom side of the CPIP5430 and tighten the screws 9 Reinstall the CPIP5430 in its proper slot Be sure the module is well seated in the backplane connectors 10 If necessary connect the system to its AC or DC power source and turn the power on Note The rear I O signals on the J6 pins of the PMC 1 slot are routed to the J3 connector on ...

Page 33: ... for both pin and component integrity When installing payload boards we recommend that you start at the left of the cardcage and work to the right Installation into a fully populated chassis should be performed with caution to avoid damage to the pins and components located on the front or back sides of the board especially when installing the final boards Installing a Board MCG and our suppliers ...

Page 34: ...al board ejector handles used with the MXP platform A Elma Latching B Rittal Type II C Rittal Type IV All handles are compliant with the CompactPCI specification and are designed to meet the IEEE1101 10 standards To reduce the risk of pin damage refer to the following illustration and perform these steps when installing modules Note The following illustration may not represent the exact board you ...

Page 35: ...re using your thumb if necessary to carefully slide the module into the card cage rail guides Continue to gently push until the prealignment guide pegs engage in the backplane connector receptacles Stage 2 and the ejector handle makes contact with the chassis rails DO NOT FORCE THE BOARD INTO THE BACKPLANE SLOT 6 Use the ejector lever to seat the module in the slot by closing the lever inward unti...

Page 36: ...to do so shutdown may occur automatically after Step 2 is performed Likewise if system software is configured to illuminate the blue LED on the front of the module ensure this has occurred before proceeding to Step 3 Once it illuminates you may continue to remove the module 1 Loosen the module s captive screws 2 Press the red button on the ejector levers to unlock 3 Move the ejector levers in an o...

Page 37: ...banner and then runs a memory test Indicators There are three LEDs and one reset switch on the front panel of the CPIP5430 Each indicator is described in the following sections LEDs for Gigabit Ethernet Port Two LED indicators on the Ethernet connector show status of the gigabit Ethernet port The yellow LED indicates speed and when illuminated it shows that the port has negotiated a 1000Mbps data ...

Page 38: ...1 microsecond to 10 minutes The system host CPU deactivates the PCI to PCI bridge before implementing the reset function The BIOS preserves as much of the system memory state as possible PXE Boot Use the following steps to boot the CPIP5430 from a PreBoot Execution Environment PXE server Note This explanation is only the sequence to get you into the PXE server environment For an explanation on how...

Page 39: ...he network controller to boot from There may be 1 2 or 3 choices If there is only one choice this is the management front panel or RTM port If there are two or more choices two will have the same XX value These are the backplane 2 16 ports the other is the management port For the 2 16 interfaces Z the port 0 or 1 Port 0 connects to switch 1 and port 1 connects to switch 2 9 Save changes and exit S...

Page 40: ......

Page 41: ...gine and help windows Upon initial power up or after a hardware reset the processor begins executing code out of the onboard BIOS The BIOS contains all of the software needed to boot the board to a working state so an operating system can be loaded The first order of business for the BIOS is to initialize crucial system components such as timers and chipset parts The BIOS then performs basic compo...

Page 42: ...information the board name and the version of the BIOS present in the system At this point the following message appears at the bottom of the screen giving the hotkey that will invoke the setup engine F2 or s Enter Setup SPACE Skip Memory ESC BOOT Menu If the F2 or s key is pressed the message below will be displayed and the BIOS Setup Engine will be entered after the option ROM scan Entering SETU...

Page 43: ...ither integrated networking components or add in cards To change the boot order of devices within a category such as to boot from IDE hard drive instead of SCSI or to permanently change the boot order you will have to enter SETUP and change the boot options If any errors are detected up to this point they will be displayed on the screen along with the following prompt to direct further actions Pre...

Page 44: ...nd Memory Addresses The Resource Manager takes on the responsibility for configuring Plug and Play PnP cards as well as system board devices during the power up phase After the Power On Self Test POST process is complete control of the Plug and Play device configuration passes from the system BIOS to the system software The BIOS does however provide configuration services for system board devices ...

Page 45: ...s you to view the current settings of each category without having to actually enter the category To execute a specific category using the up down arrow keys move the highlighted bar onto it and press Enter If you select Go To Subscreen notice that there is a different navigational menu that allows you to Select Item using the up down arrows and Change Option using the up down arrows or the keys T...

Page 46: ...STEM CONFIGURATION SUMMARY SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT Motorola CPIP5430 CPU Type Mobile Pentium R 4 M CPU 2 20GHz CPU Speed 2 20GHz IDE Drive 0 Not Detected Base RAM 632KB IDE Drive 1 Not Detected Extended RAM 1024MB IDE Drive 2 Not Detected Cache Size 512KB IDE Drive 3 Not Detected BIOS Date 04 16 04 ...

Page 47: ...ays the core version that this BIOS was built upon IDE Drive 0 3 Displays the drive type selected for each directly or RTM attached IDE drive connected to on board IDE controller COM Ports Displays the I O addresses of all installed serial ports LPT Ports Displays the I O addresses of all installed parallel ports Memory Mode Displays the operating mode for the system memory PMC Mode Displays the P...

Page 48: ...G MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT DATE TIME OPTIONS System Time 13 49 05 System Date Tue 4 27 2004 BIOS OPTIONS Quick Boot Disabled Summary Screen At Boot Disabled Boot Failure Retry Auto AddOn ROM Display Mode Force BIOS AddOn ROM Display Delay Disabled Pause on POST Errors Disabled SETUP Prompt During Post Enabled Bootup Num Lock On SYSTEM OPTIONS CPU Speed Fast MPS Revision 1 4 Sp...

Page 49: ...eases the amount of time needed to boot the system Summary Screen At Boot When this option is enabled the system summary information will be displayed before the system boots Boot Failure Retry Allows BIOS to automatically reattempt to boot if all detected boot devices fail AddOn ROM Display Mode Selects the display mode used by the BIOS when signing on option ROMs AddOn ROM Display Delay When thi...

Page 50: ...speed This option applies only to processors that support SpeedStep technology Processors that do not support SpeedStep will run at their rated speed MPS Revision Selects the MultiProcessor Specification version to which the BIOS conforms The default of 1 4 is recommended unless an OS reports a MPS error Spread Spectrum Controls the spread spectrum behavior of the system clock generator Enabling t...

Page 51: ...ce properties for the system It is also used to configure the parameters for each directly attached drive in the system HARD DRIVE CONFIGURATION UTILITY SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT IDE CONFIG PRIMARY MASTER Not Detected PRIMARY SLAVE Not Detected SECONDARY MASTER Not Detected SECONDARY SLAVE Not Detecte...

Page 52: ...onfiguration for the onboard parallel and serial IDE controllers Combined Mode Option SelectswhichIDEconnectorsareactive WhensettoP ATAPrimary the on board paralleldriveissetastheprimarymaster andtheserialATA connector on the Rear I O board is set to secondary master The parallel ATA connector on the Rear I O is disabled in this mode When set to S ATA primary the serial ATA connector on the Rear I...

Page 53: ... to 40 pin if problems are encountered in 80 pin mode PRIMARY MASTER CONFIGURATION SUMMARY IDE CONFIG PRIMARY MASTER PRIMARY SLAVE SECONDARY MASTER SECONDARY SLAVE Device Hard Disk Vendor WDC WD360GD 00FNVA0 Size 37 0GB LBA Mode Supported Block Mode 16 Sectors PIO Mode 4 Async DMA MultiWord DMA 2 Ultra DMA Ultra DMA 2 S M A R T Supported Type Auto LBA LARGE MODE Auto Block Multi Sector Transfer Mo...

Page 54: ... type of IDE device currently installed Type choices include Not Installed Hard Disk ATAPI CDROM and ARMD Vendor Displays the manufacturer device identification information Size Displays the storage capacity of the device LBA Mode Displays support for Logical Block Accessing LBA uses 28 bit addressing of the hard disk instead of CHS Cylinder Head Sector addressing for supporting drives up to 137GB...

Page 55: ...ssed during POST to display a boot device menu This will override the boot order chosen in the CMOS Setup Utility and boot from the device selected BOOT ORDER CONFIGURATION SUMMARY SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT Boot Device Priority 1st Boot Device IBA GE Slot 0210 v1 2nd Boot Device IBA GE Slot 0211 v1 3r...

Page 56: ...es The BIOS attempts to boot from items at the top of the list first Removable Devices Boot from legacy floppy diskette removable LS 120 or ZIP drives The desired removable device must be selected Hard Disk Devices Boot from hard disk drive The desired hard drive must be selected through Hard Disk Drives ATAPI CDROM Drives Boot from an IDE CDROM ...

Page 57: ...CI X Gigabit Boot ROM Enabled I O PORT CONTROL Serial Port 1 Address 3F8 IRQ4 Serial Port 2 Address 2F8 IRQ3 CONSOLE REDIRECTION BIOS Console Redirection Enabled Serial Port COM1 Serial Port Mode 19200 8 n 1 Flow Control None Redirection After BIOS POST Always Terminal Type ANSI VT UTF8 Combo Key Support Disabled Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Motorola CPIP5430 BIOS ...

Page 58: ...ntrols the boot ROM allowing for remote network booting with the 82547 Dual PCI X Gigabit This item controls the onboard 82546 PCI X gigabit chip PCI X Gigabit Boot ROM Controls the boot ROM allowing for remote network booting with the 82546 Serial Port 1 2 Address The two serial ports can be configured to one of four possible settings or disabled I O Address Interrupt COM Port 3F8h IRQ4 COM1 2F8h...

Page 59: ...e serial port to be used for console redirection Serial Port Mode Selects the baud rate for console redirection The possible baud rates are 9600 19200 38400 57600 and 115200 Flow Control This item allows flow control to be used to prevent data overruns If the cable supports hardware handshaking then the hardware option should be selected Otherwise software handshaking should be selected Redirectio...

Page 60: ...B CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT USB CONTROL USB Function Front and Rear USB 2 0 Controller Enabled Legacy USB Support Always Legacy USB Speed Full Speed USB MASS STORAGE CONFIG USB Mass Storage Reset Delay 20 Sec No USB Mass Storage device detected Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Motorola CPIP5430 BIOS v1 00 Beta M ...

Page 61: ...upport Controls whether USB devices are available after POST When set to POST Only the USB keyboard may be used during POST Storage devices are not applicable in POST Only mode since they do not need to be accessed When set to Always USB devices including drives CD ROMs keyboards and mice can be accessed after POST has completed Legacy USB Speed Selects the maximum operating speed for USB devices ...

Page 62: ...STEM SETUP HARD DISK SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT PCI OPTIONS PCI Latency Timer 64 Interrupt 19 Capture Disabled Reserved Memory Size Disabled PNP OPTIONS Plug Play O S No Reset Config Data No POWER OPTIONS ACPI 2 0 Support No ACPI APIC Support Enabled Headless Mode Disabled ACPI Console Redirection Disabled Select Screen Enter Go to Sub Scr...

Page 63: ...ock can be reserved in 16K increments from C000h to DFFFh This is not needed for PCI devices but may be needed for legacy devices that are behind an add on PCI card Plug and Play O S If disabled default the BIOS will set up all PnP devices If enabled the BIOS configures only the devices critical for booting and the operating system is assumed to configure all other PnP devices Even when set to dis...

Page 64: ...Support Enables or disables the ACPI support for the APIC When enabled a pointer to the APIC table is integrated into the RSDT pointer list Headless Mode If this item is enabled information about headless support is included in the ACPI FACP table ACPI Console Redirection Lets an ACPI OS know if it should use console redirection If enabled the BIOS informs the OS which port it should use what data...

Page 65: ...CURITY VIRUS EXIT View Event Log Mark All Events As Read Clear Event Log Event Log Statistics Disabled Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Motorola CPIP5430 BIOS v1 00 Beta M View Event Log This item is used to open a window containing a list of the currently logged system events Mark All Events As Read This item is used the mark all system events in the log as read Clear...

Page 66: ... CONFIGURATION UTILITY SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT Supervisor Password Not Installed User Password Not Installed Change Supervisor Password Change User Password Clear User Password Boot Sector Virus Protection Disabled Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Motorola CPIP5430 BIOS ...

Page 67: ...rd This item indicates whether a user password has been set Change Supervisor Password This item allows setting the supervisor password Change User Password This item allows setting the user password Clear User Password This item is used to clear the user password Boot Sector Virus Protection When this item is enabled a warning message is displayed before any program tries to access the boot secto...

Page 68: ... default settings stored in the BIOS EXIT MENU SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT Save Changes and Exit Discard Changes and Exit Load Defaults Discard Changes Save Custom Defaults Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Motorola CPIP5430 BIOS v1 00 Beta M ...

Page 69: ... Loads the SETUP factory default values Discard Changes Discard any changes made during SETUP Save Custom Defaults Allows you to make a backup of the current CMOS settings to NVRAM Load Custom Defaults Loads the SETUP Custom Defaults If custom defaults have been saved they will automatically be loaded if CMOS becomes corrupted instead of the manufacturing defaults Clear Custom Defaults Erases the ...

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Page 71: ...h J3 and J5 CPU Cache Supports Intel Mobile Pentium 4 Processor M processor with 512KB on die L2 cache at full core speed and 400 MHz FSB Chipset Intel 875P MCH with 6300 ESB ICH Supports up to 4GB of DDR memory Supports ECC on memory bus 64 bit 33 66 MHz on board PCI bus interface System Memory Supports 266 MHz to 400 MHz DDR Supports two onboard SO DIMM sockets Supports memory size up to 4GB Sup...

Page 72: ... 10 100 1000 Mbps auto negotiation On board Ethernet Management Port One Ethernet port on front panel COM1 provided by one Intel 82547EI Gigabit Ethernet controller On Communication Streaming Architecture CSA bus IEEE 802 3x compliant flow control support IEEE 802 3ab compliant 10 100 1000 Mbps auto negotiation Front panel Ethernet port can be routed to the RTM System Management Interface QLogic Z...

Page 73: ...use and Mass Storage Device ACPI 1 0 and 2 0 Plug and Play PCI 2 2 Compliant Enhanced IDE Support PIO DMA and Ultra DMA IDE S M A R T Support Custom CMOS Save to Flash Security General Features PCI Rev 2 1 compliant PICMG 2 1 CompactPCI Hot swap specification Rev 1 0 compliant PICMG 2 9 CompactPCI System Management Bus Rev 1 0 compliant PICMG 2 16 CompactPCI Packet Switching Backplane Rev 1 0 comp...

Page 74: ...4260 0604 Intel 82875P Mobil Intel Pentium 4 Processor Intel 6300 ESB ICH SIO BIOS FWH RJ 45 Front Panel Reset USB COM1 RJ45 Blue LED Intel 82547EI CSA Gig E Clock Source ZirconPM CSA DDR SO DIMM DDR SO DIMM USB COM2 USB IDE Compact Flash S ATA Drive Conn IDE Drive Conn PMC Slot 1 Intel 82546EB Dual Gig E LPC HI 1 5 FSB Ch 1 Ch 0 RTM J5 PMC Slot 2 PIM J3 2 16 J3 J1 J2 64 66 PCI VRD MUX ...

Page 75: ...o Appendix C IPMI Commands Asynchronous Serial Ports Two serial ports are supported on the CPIP5430 The EIA232 drivers and receivers reside on board the CPIP5430 COM1 is resides on the board and is available via an RJ45 connector on the front panel COM2 resides on the RTM and is available via an RJ45 connector on the RTM front panel By default the BIOS configures the primary port COM1 for use by R...

Page 76: ...orted by a 256 byte battery backed RAM Watchdog Timer SIO Chip The 6300 ESB ICH provides a two stage watchdog timer with independent count values for each stage The first stage generates an INT or SMI The second stage drives an external pin active until it is cleared by system reset or a power cycle It is configurable for granularity from 1us to 10 min Table 4 2 Serial Port Characteristics Serial ...

Page 77: ...dware monitor via I2C 2 Three serial EEPROMs for boot and runtime firmware SEL FRU and customer use QLogic provides a firmware suite that supports the Intelligent Platform Management Interface IPMI specification including the Intelligent Platform Management Bus IPMB The supporting firmware features are summarized as follows IPMI version 1 0 Online firmware update via IPMI standard command Dynamic ...

Page 78: ...he PCI request arbitration assignments for the PCI bus 1 are as follows Table 4 3 PCI Bus 1 Arbitration Assignments PCI Bus Request PCI Master s Request 0 Onboard LAN 82546EB Request 1 PMC slot 1 1st REQ Request 2 PMC slot 1 2nd REQ Request 3 PMC slot 2 Request 4 None Request 5 None ...

Page 79: ...s installed directly in the MXP backplane in the rear transition board slot of the chassis and interfaces with the CPIP5430 board through the J3 and J5 connectors This RTM does not support hot swap and it can be serviced if the front CPIP5430 SBC is removed or powered off Rear panel connectors include One RJ45 connector for 10 100 1000 Base Tx Ethernet Two USB ports One RJ45 connector for asynchro...

Page 80: ...lock Diagram Figure 5 1 shows a block diagram of the overall RTM architecture Figure 5 1 CPIP5430 RTM1 Block Diagram 4261 0404 RS232 Transceiver PIM mag Copper RJ45 Gigabit copper I O Serial ATA Signal Connector Compact Flash 50 pin socket COMM USB 40 pin USB USB Power I2C EEprom IDE External Connector Comm USB 2 3OC USB Gigabit IPMI s ATA IDE POR LED LED 12V 12V 3 3V 5 0V PIM PMC BUS 5 0V 3 3V 64...

Page 81: ...ont panel The IDE bus on the CPIP5430 RTM1 provides one CompactFlash media socket and a 40 pin external IDE connector interface for an optional hard drive The IPMI I2 C bus provides for IPMI review of the CPIP5430 RTM1 build Vital Product Data VPD The CPIP5430 RTM1 indicates FAIL and GOOD power status via a LED on the front panel The CPIP5430 RTM1 uses 5V and 3 3V supplied from the CPIP5430 for co...

Page 82: ... The signaling occurs over two wires on each point to point segment There are three data rates The USB high speed signaling bit rate is 480 Mb s The USB full speed signaling bit rate is 12 Mb s A limited capability low speed signaling mode is 1 5 Mb s The CPIP5430 RTM1 provides the standard power resource of 0 5A at 5V to the peripherals The power to each port is protected Pin assignments are foun...

Page 83: ...the placement of the jumpers headers connectors and various other components on the CPIP5430 RTM1 The configurable headers are listed in the following table For pin assignments on the CPIP5430 RTM1 refer to Pin Assignments on page 5 9 Note Items in brackets are factory default settings Table 5 1 RTM Jumper Settings Jumper Function Setting J15 Enable VPD Write 2 3 J16 Sets the CompactFlash card as ...

Page 84: ...5430 5 Figure 5 2 CPIP5430 RTM1 Layout Table 5 2 Connector Reference Reference Designator Connector Function J3 User I O Refer to Table 5 4 for pin assignments J4 For alignment purposes only J5 User I O Refer to Table 5 3 for pin assignments J6 COM2 J7 USB J8 USB J9 1GB Ethernet ...

Page 85: ...p the ESD secured throughout this procedure 2 Shut down the operating system 3 Turn AC or DC power off and remove the AC cord or DC power lines from the system or power down or remove the CPIP5430 4 Remove the chassis or system cover s as necessary for access to the chassis backplane 5 Locate the desired peripheral slot 6 Remove any filler panel or existing board that might fill that slot J10 PMC ...

Page 86: ...to the backplane 8 Simultaneously move the injector ejector levers in an inward direction so they lock in place 9 Secure in place with the screws provided on the outside edge of each injector ejector lever Be sure the screws make good contact with the transverse mounting rails to minimize RF emissions 10 Connect the appropriate cables to the rear of the transition module 11 Replace the chassis or ...

Page 87: ...purposes only Table 5 3 J5 User I O Connector PO S Row A Row B Row C Row D Row E Row F 22 DA2 CS1_L CS3_L DA1 DACTV_L GND 21 DIOW_L DMACK_L DIOR_L PDIA_L DA0 GND 20 DD0 DD15 INTRQ DMARQ IORDY GND 19 DD12 DD2 DD13 DD1 DD14 GND 18 DD5 DD10 DD4 DD11 DD3 GND 17 DRESET_L DD7 DD8 DD6 DD9 GND 16 RSVD RSVD GND RSVD RSVD GND 15 RSVD GND RSVD GND RSVD GND 14 RSVD RSVD RSVD RSVD RSVD GND 13 5 0V_IN 5 0V_IN 1...

Page 88: ...DD0 GND 16 LP_B_DA1 LP_B_DA1 GND LP_B_DC1 LP_B_DC1 GND 15 LP_B_DB1 LP_B_DB1 GND LP_B_DD1 LP_B_DD1 GND 14 3 3V_IN 3 3V_IN 3 3V_IN 5 0V_IN 5 0V_IN GND 13 PMCIO53 PMCIO28 PMCIO27 PMCIO2 PMCIO1 GND 12 PMCIO54 PMCIO30 PMCIO29 PMCIO4 PMCIO3 GND 11 PMCIO55 PMCIO32 PMCIO31 PMCIO6 PMCIO5 GND 10 PMCIO56 PMCIO34 PMCIO33 PMCIO8 PMCIO7 GND 9 PMCIO57 PMCIO36 PMCIO35 PMCIO10 PMCIO9 GND 8 PMCIO58 PMCIO38 PMCIO37 ...

Page 89: ... PMCIO64 PMCIO50 PMCIO49 PMCIO24 PMCIO23 GND 1 _5V_IN PMCIO52 PMCIO51 PMCIO26 PMCIO25 GND Table 5 4 J3 User I O Connector continued POS Row A Row B Row C Row D Row E Row F Table 5 5 PMC Connector J10 Pin Assignments Pin Signal Signal Pin 1 PMCIO1 PMCIO2 2 3 PMCIO3 PMCIO4 4 5 PMCIO5 PMCIO6 6 7 PMCIO7 PMCIO8 8 9 PMCIO9 PMCIO10 10 11 PMCIO11 PMCIO12 12 13 PMCIO13 PMCIO14 14 15 PMCIO15 PMCIO16 16 17 P...

Page 90: ... PMCIO45 PMCIO46 46 47 PMCIO47 PMCIO48 48 49 PMCIO49 PMCIO50 50 51 PMCIO51 PMCIO52 52 53 PMCIO53 PMCIO54 54 55 PMCIO55 PMCIO56 56 57 PMCIO57 PMCIO58 58 59 PMCIO59 PMCIO60 60 61 PMCIO61 PMCIO62 62 63 PMCIO63 PMCIO64 64 Table 5 6 J14 PMC Power Pin Assignments Pin Signal Signal Pin 1 Signal reserved 12V 2 3 Signal reserved Signal reserved 4 5 5V Signal reserved 6 7 Signal reserved Signal reserved 8 T...

Page 91: ...ignal reserved Signal reserved 28 29 GND Signal reserved 30 31 Signal reserved Signal reserved 32 33 Signal reserved GND 34 35 Signal reserved Signal reserved 36 37 5V Signal reserved 38 39 Signal reserved Signal reserved 40 41 Signal reserved 3 3V 42 43 Signal reserved Signal reserved 44 45 GND Signal reserved 46 47 Signal reserved Signal reserved 48 49 Signal reserved GND 50 51 Signal reserved S...

Page 92: ...ignal reserved Signal reserved 60 61 12V Signal reserved 62 63 Signal reserved Signal reserved 64 Table 5 6 J14 PMC Power Pin Assignments continued Pin Signal Signal Pin Table 5 7 IDE Connect Pin Assignment Pin Signal Signal Pin 1 Reset Gnd 2 3 D7 D8 4 5 D6 D9 6 7 D5 D10 8 9 D4 D11 10 11 D3 D12 12 13 D2 D13 14 15 D1 D14 16 17 D0 D15 18 19 Gnd Key 20 21 21 Gnd 22 23 IOW Gnd 24 25 IOR Gnd 26 27 IOCH...

Page 93: ...t DMACK_L DMA acknowledge DIOR_L I O read DIOW_L I O write IORDY indicates drive ready for I O DD 15 0 data lines DRESET_L reset signal to drive CS1FX_L chip select drive 0 or command register block select CS3FX_L chip select drive 1 or command register block select DA 2 0 drive register and data port address lines INTRQ drive interrupt request Table 5 7 IDE Connect Pin Assignment continued Pin Si...

Page 94: ...ly 5 V at the source VBUS is protected against external faults by a resetable fuse Control of the USB output power is controlled by the host board Table 5 8 RTM COM2 Pin Assignments Pin Signal Function 1 DCD Data Carrier Detect 2 RTS Request to Send 3 GND Ground 4 TXD Transmit Data 5 RXD Receive Data 6 GND Ground 7 CTS Clear to Send 8 DTR Data Terminal Ready Table 5 9 RTM USB Port 2 Pin Assignment...

Page 95: ...rnet ports RJ45 provide the status LEDs for the RTM CompactFlash The following pin assignments apply to the Type II 50 pin CompactFlash connector on the CPIP5430 RTM1 Table 5 10 RTM Ethernet Connector Pin Assignments Pin 1000 Mb s 10 100 Mb s 1 MDIO_0 TD 2 MDIO_0 TD 3 MDIO_1 RD 4 MDIO_2 Not Used 5 MDIO_2 Not Used 6 MDIO_1 RD 7 MDIO_3 Not Used 8 MDIO_3 Not Used Table 5 11 CompactFlash Connector Pin...

Page 96: ...ND DA2 18 19 DA1 DA0 20 21 DD0 DD1 22 23 DD2 NC 24 25 NC NC 26 27 DD11 DD12 28 29 DD13 DD14 30 31 DD15 DC3_L 32 33 NC SDIOR_L 34 35 DIOW_L 5 0V 36 37 IRQ 5 0V 38 39 CSEL_L NC 40 41 BRSTDRV_L DIORDY 42 43 DREQ DACK_L 44 45 DASP_L PDIAG_L 46 47 DD8 DD9 48 49 DD10 GND 50 Table 5 11 CompactFlash Connector continued Pin Signal Signal Pin ...

Page 97: ...with the signal cable receptacle and the other end of the cable is inserted into the RTM on board signal connector The signal cable wire consists of two twinax sections in a common outer sheath In addition to the signal cable there is a separate power cable for the cabled connection The RTM will not provide the Serial ATA power cable connection Figure 5 3 Serial ATA Connection Pin Assignment ...

Page 98: ...x and is received by the SATA disk drive Rx These signals must be 100 ohms differential characteristic impedance as per the Serial ATA 1 0 specification IO_SATA_Rx 15 0 Differential SATA signal pair that originates at the SATA disk drive Tx and is received by the I O controller Rx These signals must be 100 ohms differential characteristic impedance As per the Serial ATA 1 0 specification ...

Page 99: ...MC bus connects to the internal PCI bus bus 1 which is 64 bits wide There are four 64 pin EIA E700 AAAB SMT connectors for the first 64 bit PMC slot with feature connector for PIM pinout and there are three 64 pin EIA E700 AAAB SMT connectors for the second 64 bit PMC slot without feature connector on the CPIP5430 Note For all PMC Connectors PCI_RSVD PCI Reserved Pin Table 6 1 PMC Connector J9 J11...

Page 100: ...8 29 AD19 5V 30 31 VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 PCI_RSVD PCI_RSVD 42 43 PAR GND 44 45 VIO AD15 46 47 AD12 AD11 48 49 AD09 5V 50 51 GND C BE0 52 53 AD06 AD05 54 55 AD04 GND 56 57 VIO AD03 58 59 AD02 AD01 60 61 AD00 5V 62 63 GND REQ64 64 Table 6 1 PMC Connector J9 J11 Pin Assignments Pin Signal Signal Pin ...

Page 101: ...O 4 5 TDI GND 6 7 GND PCI_RSVD 8 9 PCI_RSVD PCI_RSVD 10 11 PRESENT 3 3V 12 13 PCI_RRESET PRESENT 14 15 3 3V PRESENT 16 17 PME GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL AD23 26 27 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND PMC_RSVD1 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD8 3 3V 50 ...

Page 102: ...ments 6 Note 51 AD7 PMC_RSVD2 52 53 3 3V PMC_RSVD3 54 55 PCI_RSVD GND 56 57 PCI_RSVD PCI_RSVD 58 59 GND PCI_RSVD 60 61 ACK64 3 3V 62 63 GND PCI_RSVD 64 1 J7 2nd IDSEL 2 J7 2nd PCI REQ 3 J7 2nd PCI GNT Table 6 2 PMC Connector J5 J7 Pin Assignments Pin Signal Signal Pin ...

Page 103: ... 1 PCI_RSVD GND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 VIO AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 ...

Page 104: ...b Site Connector Pin Assignments 6 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 D33 GND 56 57 VIO AD32 58 59 PCI_RSVD PCI_RSVD 60 61 PCI_RSVD GND 62 63 GND PCI_RSVD 64 Table 6 3 PMC Connector J8 J10 Pin Assignments Pin Signal Signal Pin ...

Page 105: ...9 PMCIO9 PMCIO10 10 11 PMCIO11 PMCIO12 12 13 PMCIO13 PMCIO14 14 15 PMCIO15 PMCIO16 16 17 PMCIO17 PMCIO18 18 19 PMCIO19 PMCIO20 20 21 PMCIO21 PMCIO22 22 23 PMCIO23 PMCIO24 24 25 PMCIO25 PMCIO26 26 27 PMCIO27 PMCIO28 28 29 PMCIO29 PMCIO30 30 31 PMCIO31 PMCIO32 32 33 PMCIO33 PMCIO34 34 35 PMCIO35 PMCIO36 36 37 PMCIO37 PMCIO38 38 39 PMCIO39 PMCIO40 40 41 PMCIO41 PMCIO42 42 43 PMCIO43 PMCIO44 44 45 PMC...

Page 106: ...e J6 signals are connected to the CompactPCI J3 connector To use those signals the RTM needs to be custom designed for special purpose or to have a PIM connector on board 49 PMCIO49 PMCIO50 50 51 PMCIO51 PMCIO52 52 53 PMCIO53 PMCIO54 54 55 PMCIO55 PMCIO56 56 57 PMCIO57 PMCIO58 58 59 PMCIO59 PMCIO60 60 61 PMCIO61 PMCIO62 62 63 PMCIO63 PMCIO64 64 Table 6 4 PMC Connector J6 Pin Assignments Pin Signal...

Page 107: ...akes to the backplane Table 6 5 Power Connector J1 Pin Assignments Pin Z A B C D E F 25 GND 5 0V ENUM 3 3V 5 0V GND 24 GND 5 0V V IO 1 GND 23 GND 3 3V 5 0V1 GND 22 GND GND 3 3V1 GND 21 GND 3 3V GND 20 GND GND V IO GND 19 GND 3 3V GND1 GND 18 GND GND 3 3V GND 17 GND 3 3V IPMB_SCL IPMB_SDL GND1 GND 16 GND GND V IO GND 15 GND 3 3V BDSEL GND KEY GND GND 11 GND GND1 GND 10 GND GND 3 3V GND 9 GND GND1 G...

Page 108: ...tor J1 Pin Assignments continued Pin Z A B C D E F Table 6 6 Ground Connector J2 Pin Assignments Pin Z A B C D E F 22 GND GA4 GA3 GA2 GA1 GA0 GND 21 GND GND GND 20 GND GND GND GND 19 GND GND GND 18 GND GND GND 17 GND GND GND 16 GND RSVD GND GND 15 GND GND RSVD GND 14 GND GND GND 13 GND GND V IO GND 12 GND GND GND 11 GND GND V IO GND 10 GND GND GND 9 GND GND V IO GND 8 GND GND GND 7 GND GND V IO GN...

Page 109: ... GND LPb_DB1 LPb_DB1 GND LPb_DD1 LPb_DD1 GND 14 GND 3 3V 3 3V 3 3V 5V 5V GND 13 GND PMCIO53 PMCIO28 PMCIO27 PMCIO2 PMCIO1 GND 12 GND PMCIO54 PMCIO30 PMCIO29 PMCIO4 PMCIO3 GND 11 GND PMCIO55 PMCIO32 PMCIO31 PMCIO6 PMCIO5 GND 10 GND PMCIO56 PMCIO34 PMCIO33 PMCIO8 PMCIO7 GND 9 GND PMCIO57 PMCIO36 PMCIO35 PMCIO10 PMCIO9 GND 8 GND PMCIO58 PMCIO38 PMCIO37 PMCIO12 PMCIO11 GND 7 GND PMCIO59 PMCIO40 PMCIO3...

Page 110: ...D0 DD15 INTRQ DMARQ IORDY GND 19 GND DD12 DD2 DD13 DD1 DD14 GND 18 GND DD5 DD10 DD4 DD11 DD3 GND 17 GND DRESET DD7 DD8 DD6 DD9 GND 16 GND RSVD RSVD GND RSVD RSVD GND 15 GND RSVD GND RSVD GND RSVD GND 14 GND RSVD RSVD RSVD RSVD RSVD GND 13 GND 5V 5V 5V 3 3V 3 3V GND 12 GND RSVD RSVD GND GND GND GND 11 GND RSVD RSVD RSVD RSVD RSVD GND 10 GND USB 2 USB 2 GND USB 3 USB 3 GND 91 GND BI DA BI DA GND BI ...

Page 111: ...ity to 5385 100BaseTX interface vs std arrangement as in J3 Rows 15 16 and 17 18 2 USB_CTRL 12V via SBC jumper header for backward compatibility with RTM 4 GND GND 3 GND GND 2 GND RSVD RSVD RSVD RSVD RSVD GND 1 GND IPMB_CLK IPMB_DAT IPMB_PWR USB_CTRL2 USB_OC GND Table 6 8 User I O J5 Connector Pin Assignments continued Pin Z A B C D E F ...

Page 112: ...is for development service and setup operations only Serial Port COM1 Connector the CPIP5430 has one serial port RJ45 connector on the front panel with the following pin assignments It is configured as DTE Table 6 9 Front USB J14 Connector Pin Assignments Pin Signal 1 VCC 2 DATA 3 DATA 4 GND Table 6 10 COM1 J17 Pin Assignments Signal Direction 1 DCD Input 2 RTS Output 3 GNDC N A 4 TXD Output 5 RXD...

Page 113: ...P5430 has one front panel Gigabit Ethernet connector It is an industry standard RJ45 connector with the following pin assignments Table 6 11 10 100 1000Mb s J16 Connector Pin Assignments Pin 1000 Mbit s 10 100 Mbit s 1 MDIO0 TD 2 MDIO0 TD 3 MDIO1 RD 4 MDIO2 Not Used 5 MDIO2 Not Used 6 MDIO1 RD 7 MDIO3 Not Used 8 MDIO3 Not Used ...

Page 114: ... DD11 Data11 11 DD3 Data3 12 DD12 Data12 13 DD2 Data2 14 DD13 Data13 15 DD1 Data1 16 DD14 Data14 17 DD0 Data0 18 DD15 Data15 19 GND Ground 20 NC key pin 21 DDREQ Request 22 GND Ground 23 DIOWJ I O Write 24 GND Ground 25 DIORJ I O Read 26 GND Ground 27 IORDY I O Ready 28 CSEL Cable Select 29 DDACKJ DMA Acknowledge 30 GND Ground 31 IRQ14 Interrupt Request 32 NC No Connect 33 DA1 Device Address 1 34 ...

Page 115: ...C nonoperating derated 1 C per 1000 ft or 305 m above sea level Note For a 2 2 GHz CPU board with 500 LFM airflow or less the CPU performance will reduce if the chassis ambient temperature exceeds 50 C Humidity Operating 5 to 95 104 F 40 C noncondensed Humidity Nonoperating 0 to 95 104 F 40 C noncondensed Operating Altitude 16 404 ft 5 000 meters maximum Storage Altitude shipping 40 000 feet 12195...

Page 116: ...sed on model selected Shock 15G peak to peak 11ms duration 3 axis 3 times axis nonoperating Reliability MTBF 139 000 hours for CPU with 1 5GB memory at 25 C MIL HDBK 217F Compliance CE FCC Class A Designed to meet NEBs 3 0 requirements Materials All plastic PCB and battery material are UL 94V0 certified Table A 2 CPIP5430 SBC and RTM Power Requirements Configurations 5V 5 3 3V 5 12V 5 12V 5 Typ Ma...

Page 117: ...ables on all external I O ports Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground Front panel screws properly tightened For minimum RF emissions it is essential that the conditions above be implemented Failure to do so could com...

Page 118: ......

Page 119: ...tem configuration It identifies thermally significant components and lists the corresponding maximum allowable component operating temperatures It also provides example procedures for component level temperature measurements Thermally Significant Components The following table summarizes components that exhibit significant temperature rises These are the components that should be monitored in orde...

Page 120: ... Figure B 1 Thermally Significant Components Primary Side Table B 1 Thermally Significant Components Reference Designator Generic Description Max Allowable Component Temperature deg C Measurement Location U8 Perntium 4 Mobile CPU 100 C Tj U8 U27 875P MCH 95 C Tj U27 4263 0304 J5 J3 J2 J1 PMC2 U27 J13 U28 U22 J9 J5 J8 RST U18 USB J14 U30 HS PMC1 J11 J7 J10 J6 J12 J18 U25 U26 U29 U21 U23 J17 COM1 J1...

Page 121: ...een reached Measuring Junction Temperature Some components have an on chip thermal measuring device such as a thermal diode For instructions on measuring temperatures using the on board device refer to the component manufacturer s documentation listed in Appendix E Related Documentation Measuring Case Temperature Measure the case temperature at the center of the top of the component Make sure ther...

Page 122: ...ion B Note Machining a heatsink base reduces the contact area between the heatsink and the electrical component You can partially compensate for this effect by filling the machined areas with thermal grease The grease should not contact the thermocouple junction ...

Page 123: ...NK BOTTOM VIEW ISOMETRIC VIEW Machined groove for thermocouple wire routing Thermocouple junction bonded to component Heatsink base Thermal pad Through hole for thermocouple junction clearance may require removal of fin material Also use for alignment guidance during heatsink installation Machined groove for thermocouple wire routing ...

Page 124: ...rature by placing the thermocouple downstream of the component This method is conservative since it includes heating of the air by the component The following figure illustrates one method of mounting the thermocouple Figure B 3 Measuring Local Air Temperature Thermocouple junction PWB Tape thermocouple wire to top of component Air flow ...

Page 125: ...r the CPIP5430 Table C 1 CPIP5430 Memory Maps Descriptor Start Address Address Length Address Type 0 0000 0000 9FC00 1 1 0009 FC00 400 2 2 000E 0000 20000 2 3 0010 0000 1FEF 0000 1 4 1FFF 0000 F000 3 ACPI 5 1FFF FC00 1000 4 6 FEC0 0000 100000 2 7 FEE0 0000 1000 2 8 FFB0 0000 500000 2 ...

Page 126: ...ble C 2 PCI Configuration Mapping PCI Bus Device Number Field PCI Address Line Function Number IDSEL Connection Functions 0 15 AD31 0 6300ESB 0 15 AD31 1 IDE Controller 0 15 AD31 2 USB Controller 0 15 AD31 3 LPC Function subtractive decoding 1 1 AD18 0 Onboard LAN 82546EB 1 2 AD24 0 PMC Slot 1 1st ID 1 3 AD25 0 PMC Slot 1 2nd ID 1 3 AD26 0 PMC Slot 2 ...

Page 127: ...US Note ID of SO DIMM 1 4 are selected by two GPIO from CSB SO DIMM selection table Table C 3 SMBUS Address Map Address Function Device A0h SO DIMM ID SO DIMM 00h Temperature Monitor MAX1617 A0h Boot FRU data storage IPMI 24C256 A2h Runtime data storage IPMI 24C512 AAh BIOS CMOS storage 24C02 A4h VPD data storage IPMI 24C64 GPIO13 GPIO12 DIMM 0 0 1 0 1 2 1 0 3 1 1 4 ...

Page 128: ... controller s slot location Table C 4 CompactPCI Peripheral Address Map Geo Addr IPMB Addr Geo Addr IPMB Addr 0 Disabled 16 D0h 1 B0h 17 D2h 2 B2h 18 D4h 3 B4h 19 D6h 4 B6h 20 D8h 5 B8h 21 DAh 6 BAh 22 DCh 7 BCh 23 DEh 8 BEh 24 E0h 9 C0h 25 E2h 10 C4h 26 E4h 11 C6h 27 E6h 12 C8h 28 E8h 13 CAh 29 EAh 14 CCh 30 ECh 15 CEh 31 Disabled ...

Page 129: ...CI Interrupt Connections Device PCI Slot Interrupt INTA PCI Slot Interrupt INTB PCI Slot Interrupt INTC PCI Slot Interrupt INTD IOAPIC IOAPIC PIN LAN82546EB INTG INTG INTG INTG 2 2 2 2 2 3 0 1 PMC Slot 1 INTG INTG INTG INTG 2 2 2 2 0 1 2 3 PMC Slot 2 INTG INTG INTG INTG 2 2 2 2 2 3 0 1 IDE INTC 1 18 SMBUS INTB 1 17 USB1 INTA 1 16 USB2 INTD 1 19 Watchdog 2 10 USB 2 0 INTH 1 23 Intel82547 INTC 1 18 ...

Page 130: ...uch as voltages and system temperature that are indicated by the following table Table C 6 Sensor Data Record List Sensor Number Sensor Name Device Normal Reading Remark 0x20 Vcore Zircon 1 3V 0x21 5V Zircon 5V 0x22 3 3V Zircon 3 3V 0x24 12V Zircon 12V 0x11 Int temp MAX1617 30 C Temp inside MAX1617 0x13 CPU temp MAX1617 45 C ...

Page 131: ...n this release of the CPIP5430 These commands may be used by a host device driver and or application software to communicate with the Zircon sensors and other management controllers in the system SDR Sensor Data Record Device Commands Zircon firmware supports only the repository updates During SDR update only also called modal mode the commands listed below are supported Commands not supported dur...

Page 132: ......

Page 133: ... your convenience a source for the listed document is also provided It is important to note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table E 1 Related Documents Document Title Part Number MXP IPMI Subsystem Reference Manual MXPIPMIA RM MXP IPMI Library Reference Manual MXPAPIA RM Table E 2 Related Specifications...

Page 134: ...ification 2 0 Revision 3 0 PICMG 2 0 R 3 0 Dated 10 1 99 PCI Local Bus Specification Revision 2 2 PICMG 2 2 Dated 12 8 98 CompactPCI Hot Swap Specification 2 1 Revision 2 0 PICMG 2 1 R2 0 Dated 1 17 01 CompactPCI Computer Telephony Specification 2 5 Revision 1 0 PICMG 2 5 R1 0 CompactPCI System Management Bus Specification 2 9 Revision 1 0 PICMG 2 9 R1 0 Rev 2 0 Dated 2 2 00 CompactPCI Packet Back...

Page 135: ...3 boot order description 3 16 Boot Order menu 3 15 C card cage rail guide 1 15 check power supply voltage of chassis 2 1 chipset description 4 1 COM2 transition module 5 4 comments sending xvii compliance ACPI 3 24 ejector levers 1 16 EMC A 3 IPMI 4 7 PCI 4 3 PICMG 1 1 1 4 4 3 Plug Play 3 4 component descriptions 4 1 component layout 1 6 component layout transition module 5 6 configuration menus b...

Page 136: ... 4 5 4 7 form factor 4 1 front panel description 4 3 front panel status indicators 2 1 FRU information 4 5 functional descriptions 4 1 G gigabit Ethernet 4 2 gigabit Ethernet on RTM 5 3 gigabit Ethernet port 2 1 H hard disk drive on transition module 5 1 Hard Drive menu 3 11 hard drive setup description 3 14 hard drive support 1 11 heartbeat timer 4 7 hot swap and transition modules 5 1 hot swap c...

Page 137: ... 6 10 I O connector 5 9 6 11 IDE connector 5 14 PMC connectors 5 11 6 1 power connector 6 9 S ATA connector 5 19 transition module 5 9 to 5 20 USB connector 6 14 USB port 2 connector 5 16 pin assignments CPIP5430 6 1 to 6 16 PMC installation 1 13 PMC sites 1 11 PMC voltage requirements 1 13 PnP options descriptions 3 23 ports gigabit Ethernet 2 1 USB 4 2 power supply voltage check 2 1 power up sys...

Page 138: ... 1 system options description 3 10 System Setup menu 3 8 system summary description 3 7 T terminal type supported 3 19 timer heartbeat 4 7 tools for installation 1 2 transition module block diagram 5 2 bus interfaces 5 3 COM2 port 5 1 CompactFlash socket 5 3 Ethernet connector 5 1 5 3 IDE 5 1 IDE channel 5 4 PMC module 5 2 serial EEPROM 5 5 serial port 5 4 USB port 5 4 USB ports 5 1 VPD review 5 3...

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