BenQ
Rev 1.0
90dB gain control range with 2dB step size. The baseband filtering in
each channel comprises a single RC low pass filter at the input of the
first switched gain stage and two 2nd order Butterworth filters, one at
the input of each of the other switched gain stages. The R/C filter
requires an off-chip capacitor for each channel. The Butterworth filters
are fully integrated on-chip. The baseband PGA includes a DC offset
cancellation system. The auto calibration system uses a successive
approximation technique and requires around 20ms to perform a
three-stage calibration. The system calibrates out the offsets arising in
both I and Q receives channels.
Transmitter Operation
The HD155156NP generates a modulated signal at IF with a
quadrature modulator and converts it to final frequency with an Offset
Phase Locked Loop (OPLL). This allows the output frequency to be
different from the comparison frequency without affecting the normal
operation of the loop. Phase/frequency changes in the reference signal
are not scaled, as they would be if a divider were used in the feedback
path, hence the modulation is faithfully reproduced at the final
frequency. The main advantage of the OPLL in this application is that it
forms a tracking band pass filter around the modulated signal. This is
because the loop cannot respond to phase variations at the reference
that are outside its closed loop bandwidth. Thus the broadband phase
noise from the quadrature modulator is shaped by the frequency
response of the closed loop allowing the TX noise specification to be
met without further filtering. A secondary advantage of the OPLL is that
the output signal, coming from a VCO, is truly constant envelope. This
removes the problem of spectral spreading caused by AM to AM and
AM to PM conversion in the power amplifier.
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The current output allows an integrator to be included in the passive
loop filter. This is similar to the technique commonly used in PLL
synthesizers. A digital phase detector is used to speed OPLL locking.
After locking, the digital phase detector is switched off and the
analogue phase detector becomes active. The closed loop bandwidth
of the OPLL should be designed to be around 1.0 ~ 1.5MHz. The
bandwidth should be large enough to allow rapid locking and accurate
tracking of the modulation. If the bandwidth is too large, the OPLL will
Summary of Contents for C200
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