11
CPU MODULE PROCESSING TIME
11.1 Scan Time
11.1.2 Time required for each processing included in scan time
11
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(11)Latch processing time of device data
Note8
The scan time will be prolonged by the time shown below when the latch range is set
in the PLC parameter device setting.
*1*2*3
The definition of N1, N2, and N3 in the following table is as follows:
• N1: The number of device types specified to be latched (The latch range (1) and
the latch range (2) are counted as different device types.)
• N2: The number of bit devices specified to be latched
• N3: the number of word devices specified to be latched
* 1: When setting the latch range of timer (T), retentive timer (ST), and counter (C), word device one
point and bit device two points are occupied.
* 2: Number of points setting for latch relay (L) is included.
* 3: The scan time is not prolonged even if the latch range of the file register (R, ZR), extended data
register (D), and extended link register (W) are set.
POINT
Minimize the number of latch points to reduce the scan time.
The following alternative methods can also reduce the number of latch points.
• Move data to be latched to a file register.
• Store the device data that is updated not so often to the standard ROM
using the SP.DEVST instruction. (The device data stored in the standard
ROM can be read with the S(P).DEVLD instruction.)
QCPU (Q Mode)/QnACPU Programming Manual
(Common Instructions)
Note8
Table11.18 Latch processing prolonging time
CPU module
Latch processing prolonging time
Q02UCPU
(4.0 N1) + (0.12 (N2 16 + N3)) s
Q03UDCPU, Q03UDECPU
(3.0 N1) + (0.12 (N2 16 + N3)) s
Q04UDHCPU, Q06UDHCPU, Q13UDHCPU,
Q26UDHCPU, Q04UDEHCPU, Q06UDEHCPU,
Q13UDEHCPU, Q26UDEHCPU
(3.0 N1) + (0.05 (N2 16 + N3)) s
Since the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant
CPU do not perform the processing for latch, Section 11.1.2(11) can be ignored.
Basic
High
Performance
Process
Redundant
Basic
High
Performance
Process
Note11.8 Note11.8
Note11.8
Redundant
Note11.8
