Mitsubishi Electric DD-5000, Service Manual, Page: 48 / 76

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Table 3-5-5 MD36710X (3/5) Table 3-5-5 MD36710X (4/5)
Name
AMCLK
D V D E R R
D V D S O S
DVDVALID
D V D S T R B
D V D R E Q
DVDDAT [7:0]
RAMADD [11:0]
R A M C S 0 #
R A M C S 1 #
R A M R A S #
P C L K
R A M C A S #
R A M W E #
R A M D Q M
RAMDAT [15:0]
T E S T M O D E
S C N E N B L
I C E M O D E
Pin
No.
132
143
144
146
147
148
149
151
|
154
156
|
158
38
39
42
|
47
49
|
52
54
55
56
57
59
60
61
62
64
|
67
69
|
72
74
|
79
82
83
127
139
DVD-DSP interface (13 pins)
SDRAM interface (35 pins)
TEST signal (3 pins)
Function
Audio master clock I/O. 384 fs, 256 fs,
192 fs and 128 fs of sampling
frequency can be selected
(programmable).
DVD-DSP error input (Polarity
programmable)
DVD-DSP data selector start input
(Polarity programmable)
DVD-DSP data effective input
(Polarity programmable)
DVD-DSP data bit strobe (clock)
input. Polarity programmable.
DVD-DSP data requirement output
(Polarity programmable)
DVD-DSP data input bus
SDRAM address bus output
SDRAM chip select (active low)
output. Lower bit for 2 Mbyte device.
SDRAM ship select (active low).
Upper bit for 2 Mbyte device.
Row selection of SDRAM (active low)
output
SDRAM clock output (same as
internal process clock).
Column selection of SDRAM (active
high) output
SDRAM write enable (active low)
output
SDRAM data masking (active high)
output
SDRAM bidirectional data bus
Test pin. Connects to V
DD
for normal.
Test pin. Connects to GND for normal.
Test pin. Connects to V
DD
for normal.
Name
VCLK
V M A S T E R
VDEN#
V S Y N C
H S Y N C
FI
Y [7:0]
CBLANK
C [7:0]
OSDPLT (C [4])
OSDPEL [3:0]
(C [3:0])
VCLKx2
AIN
AOUT [2:0]
S/PDIF
(AOUT [3])
ALRCLK
ABCLK
Function
VCLKx2 signal is divided by 2. Used
as a qualifier of data and sync signal.
Video master/slave selection input. At
high level, video sync in MD36710X
enters master mode. (Video sync and
clock signals are developed.) After
low level, video sync enters slave
mode. (Video sync and clock signals
are entered.)
Only during reset, setting of terminal
can be changed.
Video enable input (active low). When
active, MD 36710X develops video
data. When deasserting, pixel output
becomes 3-state condition. (But sync
and clock signals are kept to be
active.)
Input is changeable at any time but
becomes effective at the next
VCLKx2.
Vertical sync bidirectional signal pin.
Polarity and length are programmable.
Horizontal sync bidirectional signal
pin. Polarity and length are
programmable.
Field identification bidirectional signal
pin. Polarity is programmable.
At 16 bit video mode (Video 8=0),
develop luminance signals. At 8 bit
mode (Video 8=1), develop luminance
and color difference signals
multiplexed in time sequence
according to the ITU-R656 standard
(in no relation to presence of SAV and
EAV sync code).
Composite blank output. Waveforms are
programmable other than polarity.
At 16 bit video mode (Video 8=0),
develop color difference signal. At 8
bit mode (Video 8=1), m.s. line 3 pin
(c [7:5]) is not used, I.s.5 pin (C [4:0])
is used as input from external OSD
device.
On-chip OSD palette selector. Selects
OSD Palette0 at low level and OSD
Plette1 at high level.
OSD pixel input. Used as an entry
signal to on-chip OSD palette.
Main video clock input or output.
Serial input of PCM stereo audio for
A D C
Serial output of PCM stereo audio for
DAC. After reset, develop signals of
low level. Only AOUT [0] supports 24
bit sample width.
S/PDIF transmitter output. Possible to
connected to DAC as the forth audio
output (AOUT [3]). After reset,
develop signal of low level.
LR clock output of AOUT [3..0] and
AIN. Becomes square waveform in
sampling frequency. Polarity of LR is
programmable.
Bit clock output of AOUT [3..0] and
AIN. At rising/falling edges
(programmable) AOUT is developed
and AIN is latched.
Pin
No.
84
85
87
89
90
91
92
94
|
97
99
|
101
98
102
104
105
106
107
109
|
111
124
112
114
115
116
117
118
119
Digital video port (24 pins)
Digital audio port (8 pins)