MiTAC E-8590, Service Manual, Page: 33 / 252

32
LCD PC E
LCD PC E
-
-
8590 MAINTENANCE
8590 MAINTENANCE
Concurrent PCI Bus Controller
33 MHz operation
Supports up to six PCI masters
Peer concurrency
Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
Zero wait state PCI master and slave burst transfer rate
PCI to system memory data streaming up to 132Mbyte/sec (data sent to north bridge via high speed V-Link Interface)
PCI master snoop ahead and snoop filtering
Eight DW of CPU to PCI posted write buffers
Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
Four lines of post write buffers from PCI masters to DRAM
Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
Delay transaction from PCI master accessing DRAM
Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
Symmetric arbitration between Host/PCI bus for optimized system performance
Complete steerable PCI interrupts
PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs