MiTAC E-8590, Service Manual, Page: 14 / 252

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LCD PC E
LCD PC E
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8590 MAINTENANCE
8590 MAINTENANCE
The P4N266 chip set consists of the VT8703 North Bridge (664 pin BGA) and the VT8233 V-Link South Bridge
(376 pin BGA). The VT8703 (which may also be referred to as a “Host System Controller”) integrates VIA’s
VT8653 Apollo Pro266T system controller with CPU bus extensions to support Pentium 4, S3 Graphics’ Savage4
2D/3D graphics accelerator and S3 Graphics’ flat panel monitor and TV out interfaces into a single 664 BGA
package. The VT8703 provides superior performance between the CPU, DRAM, V-Link bus and internal or external
AGP 4x graphics controller bus with pipelined, burst, and concurrent operation. The VT8233 (which also may be
referred to as a “V-Link Client Controller”) is a highly integrated PCI / LPC controller. Its internal bus structure is
based on a 66 MHz PCI bus that provides 2x bandwidth compared to previous generation PCI bridge chips. The
VT8233 also provides a 266MB/sec bandwidth Host/Client V-Link interface with V-Link-PCI and V-Link-LPC
controllers. It supports five PCI slots of arbitration and decoding for all integrated functions and LPC bus.
The VT8703 supports eight banks of SDR / DDR SDRAMs up to 4 GB. The DRAM controller supports PC2100 /
PC1600 Double-Data-Rated (DDR) SDRAM but can also support standard PC133 / PC100 Synchronous DRAM
(SDR SDRAM). The DDR / SDR DRAM interface allows zero wait state bursting between the DRAM and the data
buffers at 100 / 133 MHz. The different banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M /
8M / 16M / 32M / 64M x 8/16/32 DRAMs. The DRAM controller also supports optional ECC (single-bit error
correction and multi-bit detection) or EC (error checking) capability. The DRAM controller can run either
synchronous or pseudo-synchronous with the host CPU bus.
The VT8703 host system controller supports a high speed 8-bit 66 MHz Quad Data Transfer interconnect (V-Link)
to the VT8233 South Bridge. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent
operations on each bus. Five levels (double words) of post write buffers are included to allow for concurrent CPU and
V-Link operation. For V-Link Host operation, forty-eight levels (double words) of post write buffers and sixteen
levels (double words) of prefetch buffers are included for concurrent V-Link bus and DRAM/cache accesses. When
combined the V-Link Host / Client controllers, it realizes a complete PCI sub-system and supports enhanced PCI bus
commands such as Memory-Read-Line, Memory-Read-Multiple and Memory- Write-Invalid commands to minimize