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LCD PC E
LCD PC E
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8188 MAINTENANCE
8188 MAINTENANCE
PCI Interface Signals Continue
Name Type
Description
PAR
I/O
Calculated/Checked Parity:
PAR uses “even” parity
calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity
means that the ICH4 counts the number of 1s within the 36 bits
plus PAR and the sum is always even. The ICH4 always
calculates PAR on 36 bits regardless of the valid byte enables.
The ICH4 generates PAR for address and data phases and only
guarantees PAR to be valid one PCI clock after the
corresponding address or data phase. The ICH4 drives and
tri-states PAR identically to the AD[31:0] lines except that
the ICH4 delays PAR by exactly one PCI clock. PAR is an
output during the address phase (delayed one clock) for all
ICH4 initiated transactions. PAR is an output during the data
phase (delayed one clock) when the ICH4 is the Initiator of a
PCI write transaction, and when it is the Target of a read
transaction. ICH4 checks parity when it is the Target of a PCI
write transaction. If a parity error is detected, the ICH4 will set
the appropriate internal status bits, and has the option to
generate an NMI# or SMI#.
GNT[0:4]#
GNT[5]# /
GNT[B]# /
GPIO[17]#
O
PCI Grants:
The ICH4 supports up to 6 masters on the PCI
bus. GNT[5]# is muxed with PC/PCI GNT[B]# (must choose
one or the other, but not both). If not needed for PCI or PC/PCI,
GNT[5]# can instead be used as a GPIO. Pull-up resistors are
not required on these signals. If pull-ups are used, they should
be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17]
has an internal pull-up.
PCICLK
I
NOTE: PCI Clock:
This is a 33 MHz clock. PCICLK provides
timing for all transactions on the PCI Bus.
PCIRST#
O
PCI Reset:
ICH4 asserts PCIRST# to reset devices that reside
on the PCI bus. The ICH4 asserts PCIRST# during power-up
and when S/W initiates a hard reset sequence through the RC
(CF9h) register. The ICH4 drives PCIRST# inactive a minimum
of 1 ms after PWROK is driven active. The ICH4 drives
PCIRST# active a minimum of 1 ms when initiated through the
RC register.
PLOCK#
I/O
PCI Lock:
This signal indicates an exclusive bus operation and
may require multiple transactions to complete. ICH4 asserts
PLOCK# when it performs non-exclusive transactions on the
PCI bus. PLOCK# is ignored when PCI masters are granted the
bus.
SERR#
I/OD
System Error:
SERR# can be pulsed active by any PCI device
that detects a system error condition. Upon sampling SERR#
active, the ICH4 has the ability to generate an NMI, SMI#, or
interrupt.
PCI Interface Signals Continue
Name Type
Description
PME#
I/OD
PCI Power Management Event:
PCI peripherals drive PME#
to wake the system from low-power states S1–S5. PME#
assertion can also be enabled to generate an SCI from the S0
state. In some cases the ICH4 may drive PME# active due to an
internal wake event. The ICH4 will not drive PME# high, but it
will be pulled up to VccSus3_3 by an internal pull-up resistor.
REQ[A]# /
GPIO[0]
REQ[B]# /
REQ[5]# /
GPIO[1]
I
PC/PCI DMA Request [A:B]:
This request serializes ISA-like
DMA Requests for the purpose of running ISA-compatible
DMA cycles over the PCI bus. This is used by devices such as
PCI based Super I/O or audio codecs which need to perform
legacy 8237 DMA but have no ISA bus. When not used for
PC/PCI requests, these signals can be used as General Purpose
Inputs. REQ[B]# can instead be used as the 6th PCI bus request.
GNT[A]# /
GPIO[16]
GNT[B]#
/
GNT[5]# /
GPIO[17]
O
PC/PCI DMA Acknowledges [A: B]:
This grant serializes an
ISA-like DACK# for the purpose of running DMA/ISA Master
cycles over the PCI bus. This is used by devices such as PCI
based Super/IO or audio codecs which need to perform legacy
8237 DMA but have no ISA bus. When not used for PC/PCI,
these signals can be used as General Purpose Outputs. GNTB#
can also be used as the 6th PCI bus master grant output. These
signal have internal pull-up resistors.
IDE Interface Signals
Name Type
Description
PDCS1#,
SDCS1#
O
Primary and Secondary IDE Device Chip Selects for 100
Range:
For ATA command register block. This output signal is
connected to the corresponding signal on the primary or
secondary IDE connector.
PDCS3#,
SDCS3#
O
Primary and Secondary IDE Device Chip Select for 300
Range:
For ATA control register block. This output signal is
connected to the corresponding signal on the primary or
secondary IDE connector.
PDA[2:0],
SDA[2:0]
O
Primary and Secondary IDE Device Address:
These output
signals are connected to the corresponding signals on the
primary or secondary IDE connectors. They are used to indicate
which byte in either the ATA command lock or control block is
being addressed.
6.3 Intel 82801DB I/O Controller Hub 4 (ICH4)
Summary of Contents for E - 8188
Page 6: ...5 LCD PC E LCD PC E 8188 MAINTENANCE 8188 MAINTENANCE 1 2 System Hardware Parts ...
Page 54: ...53 LCD PC E LCD PC E 8188 MAINTENANCE 8188 MAINTENANCE ...
Page 55: ...54 LCD PC E LCD PC E 8188 MAINTENANCE 8188 MAINTENANCE ...
Page 93: ...92 LCD PC E LCD PC E 8188 MAINTENANCE 8188 MAINTENANCE 1 6 1 System Power Management States 2 ...
Page 95: ...94 LCD PC E LCD PC E 8188 MAINTENANCE 8188 MAINTENANCE 1 7 1 ICH4 GPIO Definitions 2 ...
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