MIPS MIPS32 74K Series, Programming Manual

Page: 138 / 156

Programming the MIPS32® 74K™ Core Family, Revision 02.14 138
Count
9.0
IDataHi
29.1
SRSCtl
12.2
Wired
6.0
DDataLo
28.3
IDataLo
28.1
Table B.2 CP0 registers by number
Nos Register Description Page
0.0
Index
Index into the TLB array 3.8.3, p.48
1.0
Random
Randomly generated index into the TLB array 3.8.3, p.48
2.0
3.0
EntryLo0-1
Output (physical) side of TLB entry 3.12, p.49
4.0 Context Mixture of pre-programmed and BadVAddr bits which can act as an OS
page table pointer.
3.8.6, p.51
4.1
ContextConfig
Defines the bits of the
Context
register into which the high order bits of
the virtual address causing a TLB exception will be written.
3.8.6, p.51
4.2 UserLocal Kernel-writable but user-readable software-defined thread ID B.1.2, p.143
5.0 PageMask Control for variable page size in TLB entries 3.12, p.49
6.0 Wired Controls the number of fixed (“wired”) TLB entries 3.8.3, p.48
7.0 HWREna Bitmask limiting user-mode access to
rdhwr
registers 5.6, p.75
8.0 BadVAddr Address causing the last TLB-related exception 3.8.6, p.51
9.0 Count Free-running counter at pipeline or sub-multiple speed B.1.5, p.145
10.0 EntryHi High-order portion of the TLB entry 3.12, p.49
11.0 Compare Timer interrupt control B.1.5, p.145
12.0 Status Processor status and control B.1.1, p.141
12.1 IntCtl Setup for interrupt vector and interrupt priority features. 5.2, p.68
12.2 SRSCtl Shadow register set selectors 5.4, p.73
12.3 SRSMap Shadow set choice for each interrupt level in VI mode 5.4, p.73
13.0 Cause Cause of last general exception B.1.3.1, p.143
14.0 EPC Restart address from exception B.1.4, p.145
15.0 PRId Processor identification and revision 2.2, p.26
15.1 EBase Exception entry point base address and CPU/VPE ID 5.1, p.73
15.2 CDMMBase 36-bit physical base address for the Common Device Memory Map facil-
ity 3.7, p.46
16.0
Config
Legacy configuration register 2.1.1, p.22
16.1-2
Config1-2
MIPS32/64 configuration registers (caches etc) 2.1.2, p.23
16.3
Config3
Configuration register showing ASEs etc 2.1.3, p.24
16.6
Config6
Additional information about the presence of optional extensions to the
base MIPS32 architecture 2.1.4, p.25
16.7 Config7 CPU-specific configuration B.2.1, p.145
Table B.1 Register index by name (Continued)
Name Number Name Number Name Number Name Number