MIPS MIPS32 74K Series, Programming Manual

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CP0 register summary and reference
143 Programming the MIPS32® 74K™ Core Family, Revision 02.14
Status[IE]
: global interrupt enable, 0 to disable all interrupts. The
di
/
ei
instructions allow you to write this bit with-
out affecting the rest of
Status
.
B.1.2 The UserLocal register
Not interpreted by hardware, this register is suitable for a kernel-maintained thread ID whose value can be read by
user-level code with
rdhwr $29
, so long as
HWREna[UL]
is set.
UserLocal
was first implemented after the first release of the 74K family of cores. Kernels should check whether
this register is implemented by inspecting
Config3[ULRI]
, as described in Section 2.1.3 “The Config3 register” .
Use of
rdhwr $29
will cause an exception in CPUs not implementing this register, providing an opportunity for an
OS kernel to simulate it.
B.1.3 Exception control: Cause and EPC registers
B.1.3.1 The Cause register
This register records information about the last exception, and is used by low-level exception handler code to decide
what to do next. But it has a handful of writable fields too, detailed below.
Figure B.2 Fields in the Cause Register
Cause[BD] : 1 if the exception happened on an instruction in a branch delay slot; in this case EPC is set to restart exe-
cution at the branch, which is usually the correct thing to do. You need only consult Cause[BD] when you need to
look at the instruction which caused the exception (perhaps to emulate it).
Cause[TI] : last interrupt was from the on-core timer (see section below for Count Compare
Cause[CE] : if that was a "co-processor unusable" exception, this is the co-processor which you tried to use.
Cause[DC] : (writable) set 1 to disable the Count register.In some power-sensitive applications, the Count register is
not used but may still be the source of some noticeable power dissipation. This bit allows the Count register to be
stopped in such situations, for example, during low-power operation following a
wait
instruction.
Cause[PCI] : last interrupt was an overflow from the performance counters, see the PerfCnt registers.
Cause[IV] : (writable) set 1 to use a special exception entry point for interrupts. It’s quite likely that if you’re doing this,
you’re also using multiple entry points for different interrupt levels, see the IntCtl register.
Cause[WP] : (writable to zero) — remembers that a watchpoint triggered when the CPU couldn’t take the exception
because it was already in exception mode (or error-exception mode, or debug mode). Since this bit automagically
causes the exception to happen again, it must be cleared by the watchpoint exception handler.
Cause[IP7-0] : So long as the CPU is not in EIC interrupt mode, this field reflects the current state of the interrupt
request inputs to the core. When one of them is active and enabled by the corresponding Status[IM7-0] bit, an inter-
rupt may occur.
31 30 29 28 27 26 25 24 23 22 21 16 15 10 9 8 7 6 2 1 0
BD TI CE DC PCI 0 IV WP 0 IP7-2 IP1-0 0 ExcCode 0
In EIC (external int controller) mode RIPL
0