MIPS MIPS32 74K Series, Programming Manual

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74K™ core features for debug and profiling
117 Programming the MIPS32® 74K™ Core Family, Revision 02.14
The fields are:
ASIDuse
: set 1 to compare the ASID as well as the address.
BAI7-0
: "byte (lane) access ignore"
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- which sounds mysterious. But this is really an address filter.
When you set a data breakpoint, you probably want to break on any access to the data of interest. You don’t usually
want to make the break conditional on whether the access is done with a load byte, load word, or even load-word-left:
but the obvious way of setting up the address match for a breakpoint has that effect.
To make sure you catch any access to a location, you can use the address mask to disable sub-doubleword address
matching and then use
DBCn[BAI]
to mark the bytes of interest inside the doubleword: well, except that zero bits mark
the bytes of interest, and 1 bits mark the bytes to ignore (hence the mnemonic).
The
DBCn[BAI]
bits are numbered by the byte-lane within the 64-bit on-chip data bus; so be careful, the relationship
between the byte address of a datum and its byte lane is endianness-sensitive.
NoSB, NoLB
: set 0 to enable
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breakpoint on store/load respectively.
BLM7-0
: a per-byte mask for data comparison. A zero bit means compare this byte, a 1 bit means to ignore its value. Set
this field all-ones to disable the data match.
TE
: set 1 to use as trigger for "PDtrace" instruction tracing.
BE
: set 1 to activate breakpoint. This fields resets to zero, to avoid spurious breakpoints caused by random register set-
tings: don’t forget to set it!
8.1.12 Understanding breakpoint conditions
There are a lot of different fields and settings which are involved in determining when a hardware breakpoint detects
its condition and causes an exception.
In all cases, there will be no break if you’re in debug mode already... but then for a break to happen:
• For all breakpoints including instructions: all the following must be true:
1. The breakpoint control register enable bit
IBAn[BE]
/
DBAn[BE]
is set.
Figure 8.15 Fields in the hardware breakpoint control registers (IBCn, DBCn)
31 24 23 22 18 17 14 13 12 11 8 7 4 3 2 1 0
DBCn
0 ASIDuse 0 BAI7-0 NoSB NoLB 0 BLM7-0 0 TE 0 BE
31 24 23 22 3 2 1 0
IBCn
0 ASIDuse 0 TE 0 BE
28. Why are there 8 bytes, when the 74K core is a 32-bit CPU with only 32-bit general purpose registers? Well, the
DBCn[BAI]
and DBCn[BLM] fields each have a bit for each byte-lane across the data bus, and the 74K core has a 64-bit data bus (and in
fact can do 64-bit load and store operations, for example for floating point values).
29. “1-to-enable” would feel more logical. The advantage of using 0-to-enable here is that the zero value means “break on either
read or write”, which is a better default than “never break at all”.