miniDSP Ltd, Hong Kong /
/ Features and specifications subject to change without prior notice
12
2.4.4
TDM
2.4.4.1
Clocks
TDM has three clock lines. These clocks are always
outputs
. The connected circuitry must therefore be set to run in
slave mode and accept its clocks from the USBStreamer.
MCLK
The master clock for both playback and recording. This pin is an output only.
FSYNC
The frame synchronization clock. This clock is equal to the sample rate and corresponds to eight 32-
bit words. This pin is an output only.
BCLK
The bit clock (also known as shift clock or system clock). This is always equal to 256 x Fs. This pin is
an output only.
Table 3 summarizes the relation between the clocks. Be sure to double-check that connected circuitry will accept the
clocks at the frequencies listed.
Table 3. TDM clocks
Sample rate Frame Sync (FSYNC) Master clock (MCLK) Bit clock (BCLK)
44.1 kHz
44.1 kHz (one short) 22.5792 MHz
11.2896 MHz
48 kHz
48 kHz (one short)
24.576 MHz
12.288 MHz
88.2 kHz
88.2 kHz (one short) 22.5792 MHz
22.5792 MHz
96 kHz
96 kHz (one short)
24.576 MHz
24.576 MHz
