miniDSP TOSLINK/ADAT, User Manual

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miniDSP Ltd, Hong Kong / www.minidsp.com / Features and specifications subject to change without prior notice
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2.4.3 I2S
2.4.3.1 Clocks
I2S has three clock lines. These clocks are always outputs . The connected circuitry must therefore be set to run in
slave mode and accept its clocks from the USBStreamer.
MCLK The master clock for both playback and recording. This pin is always an output. Connected circuitry
can choose whether or not to use it.
LRCLK The frame synchronization clock, also known as the word clock. This clock is equal to the sampling
frequency (Fs) of the audio signal. This pin is always an output.
BCLK The bit clock (also known as shift clock or system clock). This is always equal to 64 x Fs. This pin is
always an output.
Table 2 summarizes the relation between the clocks. Be sure to double-check that connected circuitry will accept the
clocks at the frequencies and ratios listed.
Table 2. I2S clocks
Sample rate (LRCLK) Master clock (MCLK) Bit clock (BCLK) MCLK/LRCLK BCLK/LRCLK
8 kHz 24.576 MHz 512 kHz 3072 64
11.025 kHz 22.5792 MHz 705.6 kHz 2048 64
12 kHz 24.576 MHz 768 kHz 2048 64
16 kHz 24.576 MHz 1024 kHz 1536 64
32 kHz 24.576 MHz 2.048 MHz 768 64
44.1 kHz 22.5792 MHz 2.822 MHz 512 64
48 kHz 24.576 MHz 3.072 MHz 512 64
88.2 kHz 22.5792 MHz 5.6448 MHz 256 64
96 kHz 24.576 MHz 6.144 MHz 256 64
176.4 kHz 22.5792 MHz 11.2896 MHz 128 64
192 kHz 24.576 MHz 12.288 MHz 128 64