BIG 8051 Manual
23
8051 Assembly Introduction
A computer instruction is made up of an operation code (op-code) followed by either
zero, one, or two bytes of operands.
The op-code identifies the type of operation to be performed while the operands iden-
tify the source and destination of the data
If the instruction is associated with more than one operand, the format is always:
Instruction
Destination, Source
The memory map of the C8051 if the lower data RAM area. Addresses 0x00 through
0X1F are banked registers R0-R7. The active bank is controlled via bits in the Pro-
gram Status Word. From the PSW, we can conclude that the bit addressable memory
located from 0x20 through 0x2F which provides 128 bits of bit addressable memory.
The upper portion is used general purpose RAM ad can be accessed by any addressing
mode (direct or indirect)
Special function registers (SFRs) have been added to the C8051 to that of the standard
8051 for enhanced peripherals. Upper data memory and SFR memory share the same
address space but are accessed via different addressing modes (direct vs. indirect). The
SFR portion can be accessed via
direct addressing
only.
There are eight modes of addressing available on the C805. The different addressing
modes determine how the operand byte mentioned earlier to be selected.
The direct and indirect addressing modes are used to distinguish between the SFR
space and data memory space.
