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VSC8489/VSC8490/VSC8491 Evaluation Board

VPPD-03745 VSC8489/VSC8490/VSC8491 User Guide Revision 1.0

2

2

Introduction

The VSC8489, VSC8490, and VSC8491 family of devices are dual and single channel (R)XAUI to SFI PHYs. 
They support the standard 10.3125 Gbps Ethernet LAN mode per 

 as well as the 9.95328 

IEEE802.ae

Gbps WIS mode from IEEE 802.3ae Clause 50. In addition, the family supports IEEE 802.3ap and 1.25 
Gbps rates as well. Certain device variants support the IEEE 1588v2 protocol and/or MACsec protocol.

One of the goals of the VSC8489/8490/8491 evaluation board (EVB) is to enable the user to observe the 
signal quality of the SFI I/Os through SMA connectors. AC-coupling caps serves as jumpers to switch the 
10 G signals between SMAs and the SFP+ connector. The (R)XAUI side can be looped back through the 
VSC3316 crosspoint. The VSC3316 can optionally route the (R)XAUI signals to SMA connectors for 
external connections. A smaller VSC3308 crosspoint facilitates routing of multiple input and output clock 
signals.

For device variants that support IEEE 1588 and MACsec, the EVB can be used to demonstrate simple 
features. For IEEE 1588 these basic features include load/save of the time to the LTC, read the egress 
timestamp (TS) through MDIO or 1588_SPI and place the TS into the packet in one-step mode. Although 
quite limited, the EVB may be used exercise the MACsec functions of encrypt and decrypt specific 
defined frames. For more advanced IEEE 1588 and MACsec features the VSC5621EV should be used. This 
platform includes a Vitesse switch running Vitesse software on the integrated MIPs processor as well as 
both 1 Gbps and 10 Gbps IEEE 1588 and MACsec capable PHYs.

A GUI is provided for the user to control the EVB from a PC via a USB cable. The GUI allows the user to 
configure devices, access registers, and run scripts. The GUI may be used without an EVB in a 
demonstration mode to provide an introduction to the device features.

An external 5 V power supply is required to power to the EVB. On-board voltage regulators are used to 
supply the 1.0 V, 1.2 V, and 2.5 V power rails for the device and the 3.3 V power rail used for auxiliary 
components.

The default configuration of the EVB is such that one port is routed to a SFP+ connector (module not 
included) and one port is routed to SMAs. This configuration allows the user to easily connect the 
evaluation board to lab equipment such as a high speed oscilloscope, bit error rate tester, or protocol 
analyzer (i.e., IXIA, Spirent, etc.) through SMA cables or fiber.

The following sections will provide more detailed information in configuring the evaluation board and 
the features of the hardware and software associated with the board. The VSC8490EV is used 
throughout this document whereas the VSC8489EV and VSC8490EV will behave similarly.

2.1

References

The following documents provide additional information regarding the device and evaluation board.

VSC8489 Datasheet ( 

 )

http://www.vitesse.com/products/download.php?number=VSC8489

VSC8490 Datasheet ( 

 )

http://www.vitesse.com/products/download.php?number=VSC8490

VSC8491 Datasheet ( 

 )

http://www.vitesse.com/products/download.php?number=VSC8491

2.2

General Description

The evaluation board provides electrical connections via 2.92 mm SMA connectors to various signals. 
The figure below shows the evaluation board. Channel 0 is found towards the top and upper right side 
of the board while Channel 1 is available on the bottom and bottom right side.

Summary of Contents for VSC8489

Page 1: ...VSC8489 VSC8490 VSC8491 User Guide VSC8489 VSC8490 VSC8491 Evaluation Board June 2014...

Page 2: ...3 Quick Start 4 4 Hardware Options 5 4 1 Power Supply Options 5 4 2 Reference Clock Options 5 5 Software 6 5 1 USBXpress Driver Installation 6 5 2 GUI Setup 6 5 3 Main Page 7 5 4 FPGA 8 5 5 Clocking C...

Page 3: ...1 Revision History The revision history describes the changes that were implemented in this document The changes are listed by revision starting with the most current publication 1 1 Revision 1 0 Rev...

Page 4: ...1 Gbps and 10 Gbps IEEE 1588 and MACsec capable PHYs A GUI is provided for the user to control the EVB from a PC via a USB cable The GUI allows the user to configure devices access registers and run s...

Page 5: ...VSC8489 VSC8490 VSC8491 Evaluation Board VPPD 03745 VSC8489 VSC8490 VSC8491 User Guide Revision 1 0 3 Figure 1 VSC8490 Evaluation Board...

Page 6: ...nd the 5 V barrel end into J89 SW2 acts as the power on off switch Slide it to the on position Connect the USB cable to the evaluation board J86 and to a PC Insert a 10 G module into U2 Channel 0 Conn...

Page 7: ...also be powered by an external 5 V power supply Use a pair of banana cables to connect a bench style power supply capable of 4 A at 5 V to the board Connect 5 V to J90 and GND to J91 SW2 acts as the...

Page 8: ...to the EVB and the PC In order to double check that the USBXpress driver is installed and recognizing the evaluation board go to the Control Panel and click on System Hardware Device Manager Inspect t...

Page 9: ...s MDIO is the communication protocol used and Channel 0 s default port address is 30 0 1E The Mode Initialization box allows the user to choose the mode 1 G LAN 10 G WAN and 10 G LAN are the supported...

Page 10: ...ser Guide Revision 1 0 8 Figure 4 GUI Main Page 5 4 FPGA The FPGA page shown below lists all the FPGA registers Clicking on any register will show their short description along with their address defa...

Page 11: ...ified timestamp will be in the PTP packets captured by the external 10G protocol tester Egress FIFO Timestamp This block gives the timestamp of the PTP frames sent by the traffic generator The timesta...

Page 12: ...64b 66b gearbox and loopback H4 at the WIS block after the framer The other 3 loopbacks are line side loopbacks i e SFI in and looped back to SFI out This includes loopback L3 loopback L2 and loopbac...

Page 13: ...nel can be selected from the drop down selection box in the upper right Figure 8 gives an example of the Packet BIST The user must first enable the packet BIST by checking the box in the upper right E...

Page 14: ...d error checking on the selected channel along with a timer The cumulative number of bit errors and the cumulative bit error rate are displayed Stop Checker will stop the timer and polling of the erro...

Page 15: ...hese addresses Be sure that the transceiver is inserted properly otherwise the Transceiver not found message will appear after the user clicks the button After successful module reads the module infor...

Page 16: ...s to device registers They are grouped into 10 tabs To select a register click on the name in the list The register s description address read write capability and current value are displayed To write...

Page 17: ...cking on from the toolbar opens the Vitesse Command Line Interface CLI window uC Vitesse CLI From here users can load initialization files or other scripts When the button is clicked another window wi...

Page 18: ...VSC8489 VSC8490 VSC8491 Evaluation Board VPPD 03745 VSC8489 VSC8490 VSC8491 User Guide Revision 1 0 16 Figure 12 Command_Line_Interface...

Page 19: ...ed once every second The previous cumulative values of both error count and BER are shown in the cumulative box fields respectively Click Stop Checker to stop the timer The display will retain the las...

Page 20: ...0 should be 010 to select the WIS Interrupt Output feature Bits 7 5 should be 001 to setup Interrupt B from channel 1 as the source Bits 15 8 and 4 3 are don t care bits here Global GPIO_6_Config2 1Ex...

Page 21: ...dependently determine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk ass...

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