VSC8489/VSC8490/VSC8491 Evaluation Board
VPPD-03745 VSC8489/VSC8490/VSC8491 User Guide Revision 1.0
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5.5
Clocking Configuration
This page contains several panes including Output clock, VSC3308 Clock Switch, and the 1588 Block.
Figure 6 shows the Clocking page.
The Output Clock selection provides the option to enable and disable RX-Clkout (J4, J7–Channel 0 and
J20, J23–Channel 1) and TX-Clkout(J12, J15–Channel 0 and J27, J31–Channel 1) for both channels. The
channel is selected by the drop down box in the upper right corner. Enabling the output clock will both
turn on the output buffer as well as configure the output frequency based on the selected operating
mode. The 10G LAN mode supports a frequency of 161 MHz.
The VSC3308 Clock distribution device provides the option of routing different clock sources (Clk0, CLk1,
Clk2, CLk3, CLk_J42/J44, CLk_J45/J46 or VCC6_XTAL) to VSC8489/VSC8490/VSC8491 Evaluation Board
User Guide Revision 1.0 June 2014 Vitesse Proprietary and Confidential Page 13 of 23 destinations (J43,
WRef, 1588_Ref, J48/J47-SMA, XRef, SRef). In most applications, routing the A5- VCC6-XTAL (156.25
MHz) to the XREF input is desired.
The basic IEEE 1588 time stamping capabilities can be evaluated on the EVB. The following configuration
options are available.
Clock frequency can be selected as internal or external. 1588 supports external clock frequency of
125 MHz
Modes supported by 1588 are Egress, Ingress and both.
Ingress FIFO Timestamp:
Ingress timestamp will be read at the reserved bytes of the PTP packet. When only the ingress
mode is enabled, and external XAUI loopback or L1 is
selected, the modified timestamp will be in the PTP packets captured by the external 10G
protocol tester.
Egress FIFO Timestamp:
This block gives the timestamp of the PTP frames sent by the traffic generator.
The timestamp can be read using MDIO or SPI communication protocol.
This feature is unavailable for Ingress Mode.
Steps to read Timestamp:
Initialize Egress or Ingress-Egress Mode;
Enable line side loopback, L1, L2, or external XAUI from the Routing page.
Choose the communication protocol (Either MDIO or SPI).
Send PTP frames from traffic generator. For simplicity of comparison of the
loopback PTP frame and the egress timestamp captured by the PHY, it is
recommended to send a single burst of a few, say 5, PTP frames from the
traffic generator.
Hit the
button. This shows the full 26 bytes separated into the
Read
timestamp (10 bytes) and Frame Signature (16 bytes) of the first packet.
Hitting the button again will read the next packet and display the contents
in the next field.
Clear all clears the previous timestamps. It is always advisable to perform
a clear all after reading a set of timestamps.
The Local Time Counter allows loading and saving the time (in seconds and
nanoseconds) in the 1588 block. Enter the time in hex (0 to FFFFFFFF) in the
textboxes and click the Update button to Load/Save respectively. GPIO_0 and
GPIO_1 must be shorted together to make this functional.
The Add/Subtract 1ns feature adds and subtracts the appropriate textbox specified
nanoseconds to the local time.
Checking the Enable the 1 PPS Output checkbox will enable the output. With
appropriate oscilloscope triggering, the user can see the effects of shifting the 1
PPS signal.
The 1588 block is turned off by clicking Turn Off 1588 Engine. To turn the block
on again the user must initialize the mode (Egress/Ingress/Both) after choosing
the clock input.
