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VSC8489/VSC8490/VSC8491

User Guide

VSC8489/VSC8490/VSC8491 Evaluation Board

June 2014

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Summary of Contents for VSC8489

Page 1: ...VSC8489 VSC8490 VSC8491 User Guide VSC8489 VSC8490 VSC8491 Evaluation Board June 2014...

Page 2: ...3 Quick Start 4 4 Hardware Options 5 4 1 Power Supply Options 5 4 2 Reference Clock Options 5 5 Software 6 5 1 USBXpress Driver Installation 6 5 2 GUI Setup 6 5 3 Main Page 7 5 4 FPGA 8 5 5 Clocking C...

Page 3: ...1 Revision History The revision history describes the changes that were implemented in this document The changes are listed by revision starting with the most current publication 1 1 Revision 1 0 Rev...

Page 4: ...1 Gbps and 10 Gbps IEEE 1588 and MACsec capable PHYs A GUI is provided for the user to control the EVB from a PC via a USB cable The GUI allows the user to configure devices access registers and run s...

Page 5: ...VSC8489 VSC8490 VSC8491 Evaluation Board VPPD 03745 VSC8489 VSC8490 VSC8491 User Guide Revision 1 0 3 Figure 1 VSC8490 Evaluation Board...

Page 6: ...nd the 5 V barrel end into J89 SW2 acts as the power on off switch Slide it to the on position Connect the USB cable to the evaluation board J86 and to a PC Insert a 10 G module into U2 Channel 0 Conn...

Page 7: ...also be powered by an external 5 V power supply Use a pair of banana cables to connect a bench style power supply capable of 4 A at 5 V to the board Connect 5 V to J90 and GND to J91 SW2 acts as the...

Page 8: ...to the EVB and the PC In order to double check that the USBXpress driver is installed and recognizing the evaluation board go to the Control Panel and click on System Hardware Device Manager Inspect t...

Page 9: ...s MDIO is the communication protocol used and Channel 0 s default port address is 30 0 1E The Mode Initialization box allows the user to choose the mode 1 G LAN 10 G WAN and 10 G LAN are the supported...

Page 10: ...ser Guide Revision 1 0 8 Figure 4 GUI Main Page 5 4 FPGA The FPGA page shown below lists all the FPGA registers Clicking on any register will show their short description along with their address defa...

Page 11: ...ified timestamp will be in the PTP packets captured by the external 10G protocol tester Egress FIFO Timestamp This block gives the timestamp of the PTP frames sent by the traffic generator The timesta...

Page 12: ...64b 66b gearbox and loopback H4 at the WIS block after the framer The other 3 loopbacks are line side loopbacks i e SFI in and looped back to SFI out This includes loopback L3 loopback L2 and loopbac...

Page 13: ...nel can be selected from the drop down selection box in the upper right Figure 8 gives an example of the Packet BIST The user must first enable the packet BIST by checking the box in the upper right E...

Page 14: ...d error checking on the selected channel along with a timer The cumulative number of bit errors and the cumulative bit error rate are displayed Stop Checker will stop the timer and polling of the erro...

Page 15: ...hese addresses Be sure that the transceiver is inserted properly otherwise the Transceiver not found message will appear after the user clicks the button After successful module reads the module infor...

Page 16: ...s to device registers They are grouped into 10 tabs To select a register click on the name in the list The register s description address read write capability and current value are displayed To write...

Page 17: ...cking on from the toolbar opens the Vitesse Command Line Interface CLI window uC Vitesse CLI From here users can load initialization files or other scripts When the button is clicked another window wi...

Page 18: ...VSC8489 VSC8490 VSC8491 Evaluation Board VPPD 03745 VSC8489 VSC8490 VSC8491 User Guide Revision 1 0 16 Figure 12 Command_Line_Interface...

Page 19: ...ed once every second The previous cumulative values of both error count and BER are shown in the cumulative box fields respectively Click Stop Checker to stop the timer The display will retain the las...

Page 20: ...0 should be 010 to select the WIS Interrupt Output feature Bits 7 5 should be 001 to setup Interrupt B from channel 1 as the source Bits 15 8 and 4 3 are don t care bits here Global GPIO_6_Config2 1Ex...

Page 21: ...dependently determine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk ass...

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