APB Configuration Interface
UG0331 User Guide Revision 15.0
784
25
APB Configuration Interface
The SERDES interface (SERDESIF), fabric DDR system (FDDR), and microcontroller subsystem double
data rate (MDDR) controller has to be initialized properly during bootup. Each of these subsystems
contains a large number of internal registers for initialization and run-time operation. These registers are
accessed through a dedicated peripheral initialization bus often called APB configuration bus. The APB
configuration interface is compliant with AMBA APB3 protocol specification.
25.1
Functional Block Diagram Description
This section provides the detailed description of the FIC_2 (APB configuration bus) subsystem.
Figure 357 •
APB Configuration Interface and Subsystems Connectivity with MSS Master
25.1.1
Architecture Overview
The preceding figure shows the APB configuration interfaces and SERDES and DDR subsystems
connectivity with the MSS master. The AHB bus matrix FIC_2 port routes the APB configuration interface
to the FPGA fabric. The SERDES and DDR subsystems are connected through CoreSF2Config soft IP.
CoreSF2Config must be instantiated (available in the Libero SoC IP Catalog) in the FPGA fabric to allow
configuration of FDDR, SERDESIF, and MDDR.
The following tables list the APB configuration interface signals and descriptions.
AHB Bus Matrix
FIC_2
SERDESIF0
CoreSF2Config
FPGA Fabric
MSS
DDR IO
DDR I
O
Lane 0
Lane 1
Lane 2
Lane 3
Lane 0
Lane 1
Lane 2
Lane 3
LPDDR
APB
APB
FDDR
APB
SmartFusion2 SoC FPGA
MDDR
APB
MSS DDR
Bridge
HPDMA
Cache
Controller
Cortex-M3
Processor
MSS_CCC
Reset
Controller
M3_CLK
FIC_2_APB_MASTER
FIC_2_APB_M_PRESET_N
MDDR_APB_SLAVE
APB_S_PRESET_N
APB_S_PCLK
SDIF0_APB_SLAVE
APB_S_PRESET_N
APB_S_PCLK
FDDR_APB_SLAVE
APB_S_PRESET_N
APB_S_PCLK
SDIF1_APB_SLAVE
MDDR_APB_PCLK
MDDR_APB_S_PRESET_N
FIC_2_APB_M_PCLK
/4
SERDESIF1
DDR 2
DDR 3
LPDDR
DDR 2
DDR 3