LX7302 Evaluation Board
Microsemi Proprietary and Confidential. LX7302 User Guide Revision 2.0
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PCB Layout Guidelines
This section details the PCB layout guidelines for the LX7302 device and extensively references
Figure 1
. It is necessary to give due consideration to the high-current paths when laying out the
(see page 5)
PCB, particularly the following: the high switching current paths from the input filter capacitors (C12–
C14) to the upper MOSFET (Q1); Q1’s connection to the output inductor (L1); L1’s connection to the
output capacitors (C9–C11); the synchronous MOSFET (Q2 and Q3) connection to L1; C9–C11’s return
connection to Q2 and Q3; and C9–C11’s return connection to C12–C14. These critical current paths
should be on a single layer only and should not be established on multiple layers through vias.
Establishing these traces with their associated parts on the top layer is preferable, both electrically and
thermally.
The LX7302 uses the signal return (AGND) for differential sensing of the output, so it is critical that all
connections unique to AGND be isolated from the power ground connections, and that the common
ground connection point be established at the point of load only. If remote sensing is not used, establish
the common ground at C2.
An R-C network consisting of R13 and C1 is used for sensing the voltage drop across L1. Both R13 and C1
should be mounted close to L1, and their respective connections to L1 should be Kelvin-connected as
close to L1 as possible.
The signal developed across C1 should be routed back to the LX7302 IC using a differential pair.
The connections from the point of load to the LX7302’s FB and AGND pins should also be routed as a
differential pair.
Parasitic capacitance must be kept to a minimum on pins 4–7. Therefore, it is important that the RSx
programming resistors (R4–R7) be mounted as close to their respective pins as possible. It is not
recommended to use test point pads on pins 4–7.
Pins 4–8 are sensitive to noise coupling. It is recommended to not route traces carrying switching signals
near these pins or their associated resistors.
Place components R10, R11, R14, C2, C4, and C5 as close to the IC as possible.
It is recommended to use 2 oz. copper due to its increased electrical and thermal performance.
A diagram indicating critical trace widths is shown in
. The EVB silkscreen, as well
Figure 1 (see page 5)
as top and bottom layers, are shown in
through
. See
Figure 2 (see page 5)
Figure 6 (see page 9)
for a complete schematic of the EVB; see
Evaluation Board Schematic (see page 18)
Bill of Materials
for a complete list of materials used.
(see page 19)
Figure 1 • PCB Critical Traces
